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author | Jason Lowe-Power <power.jg@gmail.com> | 2015-09-16 09:35:36 -0500 |
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committer | Jason Lowe-Power <power.jg@gmail.com> | 2015-09-16 09:35:36 -0500 |
commit | f065f9941b5e3b2796ec46d1926115283edd66cd (patch) | |
tree | fd115020de8f10457614eb747c463aa5928ca7e4 /configs/learning_gem5/part1/caches.py | |
parent | 0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e (diff) | |
download | gem5-f065f9941b5e3b2796ec46d1926115283edd66cd.tar.xz |
config: Add configs scripts used in Learning gem5
Added a new directory in configs (learning_gem5) to hold the scripts that are
used in the book. See http://lowepower.com/jason/learning_gem5/ for a working
copy. For now, only the scripts in Part 1: Getting started with gem5
have been added. A separate patch adds tests for these scripts.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'configs/learning_gem5/part1/caches.py')
-rw-r--r-- | configs/learning_gem5/part1/caches.py | 127 |
1 files changed, 127 insertions, 0 deletions
diff --git a/configs/learning_gem5/part1/caches.py b/configs/learning_gem5/part1/caches.py new file mode 100644 index 000000000..fbdd1bf3c --- /dev/null +++ b/configs/learning_gem5/part1/caches.py @@ -0,0 +1,127 @@ +# -*- coding: utf-8 -*- +# Copyright (c) 2015 Jason Power +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Jason Power + +""" Caches with options for a simple gem5 configuration script + +This file contains L1 I/D and L2 caches to be used in the simple +gem5 configuration script. It uses the SimpleOpts wrapper to set up command +line options from each individual class. +""" + +from m5.objects import Cache + +import SimpleOpts + +# Some specific options for caches +# For all options see src/mem/cache/BaseCache.py + +class L1Cache(Cache): + """Simple L1 Cache with default values""" + + assoc = 2 + hit_latency = 2 + response_latency = 2 + mshrs = 4 + tgts_per_mshr = 20 + + def __init__(self, options=None): + super(L1Cache, self).__init__() + pass + + def connectBus(self, bus): + """Connect this cache to a memory-side bus""" + self.mem_side = bus.slave + + def connectCPU(self, cpu): + """Connect this cache's port to a CPU-side port + This must be defined in a subclass""" + raise NotImplementedError + +class L1ICache(L1Cache): + """Simple L1 instruction cache with default values""" + + # Set the default size + size = '16kB' + + SimpleOpts.add_option('--l1i_size', + help="L1 instruction cache size. Default: %s" % size) + + def __init__(self, opts=None): + super(L1ICache, self).__init__(opts) + if not opts or not opts.l1i_size: + return + self.size = opts.l1i_size + + def connectCPU(self, cpu): + """Connect this cache's port to a CPU icache port""" + self.cpu_side = cpu.icache_port + +class L1DCache(L1Cache): + """Simple L1 data cache with default values""" + + # Set the default size + size = '64kB' + + SimpleOpts.add_option('--l1d_size', + help="L1 data cache size. Default: %s" % size) + + def __init__(self, opts=None): + super(L1DCache, self).__init__(opts) + if not opts or not opts.l1d_size: + return + self.size = opts.l1d_size + + def connectCPU(self, cpu): + """Connect this cache's port to a CPU dcache port""" + self.cpu_side = cpu.dcache_port + +class L2Cache(Cache): + """Simple L2 Cache with default values""" + + # Default parameters + size = '256kB' + assoc = 8 + hit_latency = 20 + response_latency = 20 + mshrs = 20 + tgts_per_mshr = 12 + + SimpleOpts.add_option('--l2_size', help="L2 cache size. Default: %s" % size) + + def __init__(self, opts=None): + super(L2Cache, self).__init__() + if not opts or not opts.l2_size: + return + self.size = opts.l2_size + + def connectCPUSideBus(self, bus): + self.cpu_side = bus.master + + def connectMemSideBus(self, bus): + self.mem_side = bus.slave |