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authorSophiane Senni <sophiane.senni@gmail.com>2016-11-30 17:10:27 -0500
committerSophiane Senni <sophiane.senni@gmail.com>2016-11-30 17:10:27 -0500
commitce2722cdd97a31f85d36f6c32637b230e3c25c73 (patch)
tree72993532267d3f1f99e8519be837dd7c523a722f /configs/learning_gem5/part1
parent047caf24ba9a640247b63584c2291e760f1f4d54 (diff)
downloadgem5-ce2722cdd97a31f85d36f6c32637b230e3c25c73.tar.xz
mem: Split the hit_latency into tag_latency and data_latency
If the cache access mode is parallel, i.e. "sequential_access" parameter is set to "False", tags and data are accessed in parallel. Therefore, the hit_latency is the maximum latency between tag_latency and data_latency. On the other hand, if the cache access mode is sequential, i.e. "sequential_access" parameter is set to "True", tags and data are accessed sequentially. Therefore, the hit_latency is the sum of tag_latency plus data_latency. Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'configs/learning_gem5/part1')
-rw-r--r--configs/learning_gem5/part1/caches.py6
1 files changed, 4 insertions, 2 deletions
diff --git a/configs/learning_gem5/part1/caches.py b/configs/learning_gem5/part1/caches.py
index 87256e5d0..74999cd57 100644
--- a/configs/learning_gem5/part1/caches.py
+++ b/configs/learning_gem5/part1/caches.py
@@ -45,7 +45,8 @@ class L1Cache(Cache):
"""Simple L1 Cache with default values"""
assoc = 2
- hit_latency = 2
+ tag_latency = 2
+ data_latency = 2
response_latency = 2
mshrs = 4
tgts_per_mshr = 20
@@ -107,7 +108,8 @@ class L2Cache(Cache):
# Default parameters
size = '256kB'
assoc = 8
- hit_latency = 20
+ tag_latency = 20
+ data_latency = 20
response_latency = 20
mshrs = 20
tgts_per_mshr = 12