learning_gem5: Add config files for MSI protocol

Adds the required configuration files to run the MSI protocol. These
config files are much simpler than the current Ruby examples and follow
the pattern in the other Learning gem5 run scripts.

By default, this script runs with two CPUs and runs the recently added
thread test binary.

Currently, only SE mode is supported.

This code follows Learning gem5 Part 3.
http://learning.gem5.org/book/part3/index.html

Change-Id: I813a3153d49e47198444c38a6af30269bd1310cd
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8943
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

1 files changed, 101 insertions, 0 deletions

diff --git a/configs/learning_gem5/part3/simple_ruby.py b/configs/learning_gem5/part3/simple_ruby.py
new file mode 100644
index 000000000..bf21be9e1
--- /dev/null
+++ b/configs/learning_gem5/part3/simple_ruby.py
@@ -0,0 +1,101 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2015 Jason Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Lowe-Power
+
+""" This file creates a system with Ruby caches and executes 'threads', a
+simple multi-threaded application with false sharing to stress the Ruby
+protocol.
+
+See Part 3 in the Learning gem5 book: learning.gem5.org/book/part3
+
+IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
+           also needs to be updated. For now, email Jason <jason@lowepower.com>
+
+"""
+from __future__ import print_function
+
+# import the m5 (gem5) library created when gem5 is built
+import m5
+# import all of the SimObjects
+from m5.objects import *
+
+from msi_caches import MyCacheSystem
+
+# create the system we are going to simulate
+system = System()
+
+# Set the clock fequency of the system (and all of its children)
+system.clk_domain = SrcClockDomain()
+system.clk_domain.clock = '1GHz'
+system.clk_domain.voltage_domain = VoltageDomain()
+
+# Set up the system
+system.mem_mode = 'timing'               # Use timing accesses
+system.mem_ranges = [AddrRange('512MB')] # Create an address range
+
+# Create a pair of simple CPUs
+system.cpu = [TimingSimpleCPU() for i in range(2)]
+
+# Create a DDR3 memory controller and connect it to the membus
+system.mem_ctrl = DDR3_1600_8x8()
+system.mem_ctrl.range = system.mem_ranges[0]
+
+# create the interrupt controller for the CPU and connect to the membus
+for cpu in system.cpu:
+    cpu.createInterruptController()
+
+# Create the Ruby System
+system.caches = MyCacheSystem()
+system.caches.setup(system, system.cpu, [system.mem_ctrl])
+
+# get ISA for the binary to run.
+isa = str(m5.defines.buildEnv['TARGET_ISA']).lower()
+
+# Run application and use the compiled ISA to find the binary
+binary = 'tests/test-progs/threads/bin/' + isa + '/linux/threads'
+
+# Create a process for a simple "multi-threaded" application
+process = Process()
+# Set the command
+# cmd is a list which begins with the executable (like argv)
+process.cmd = [binary]
+# Set the cpu to use the process as its workload and create thread contexts
+for cpu in system.cpu:
+    cpu.workload = process
+    cpu.createThreads()
+
+# set up the root SimObject and start the simulation
+root = Root(full_system = False, system = system)
+# instantiate all of the objects we've created above
+m5.instantiate()
+
+print("Beginning simulation!")
+exit_event = m5.simulate()
+print('Exiting @ tick {} because {}'.format(
+         m5.curTick(), exit_event.getCause())
+     )