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authorNilay Vaish <nilay@cs.wisc.edu>2014-01-04 00:03:32 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2014-01-04 00:03:32 -0600
commit9ec59e8b691d0f2e49f0a8ea6e1284b1d9e4e669 (patch)
tree08b034c02ede3e108df5d552e0214dce9e76ce34 /configs/ruby/MESI_CMP_directory.py
parent5b1804e3bdb88aea7a198ff25617bb671cd34769 (diff)
downloadgem5-9ec59e8b691d0f2e49f0a8ea6e1284b1d9e4e669.tar.xz
ruby: remove cntrl_id from python config scripts.
Diffstat (limited to 'configs/ruby/MESI_CMP_directory.py')
-rw-r--r--configs/ruby/MESI_CMP_directory.py14
1 files changed, 0 insertions, 14 deletions
diff --git a/configs/ruby/MESI_CMP_directory.py b/configs/ruby/MESI_CMP_directory.py
index 95b4904a5..6408d1ed0 100644
--- a/configs/ruby/MESI_CMP_directory.py
+++ b/configs/ruby/MESI_CMP_directory.py
@@ -72,8 +72,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
l2_bits = int(math.log(options.num_l2caches, 2))
block_size_bits = int(math.log(options.cacheline_size, 2))
- cntrl_count = 0
-
for i in xrange(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
@@ -90,7 +88,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
prefetcher = RubyPrefetcher.Prefetcher()
l1_cntrl = L1Cache_Controller(version = i,
- cntrl_id = cntrl_count,
L1Icache = l1i_cache,
L1Dcache = l1d_cache,
l2_select_num_bits = l2_bits,
@@ -119,8 +116,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
- cntrl_count += 1
-
l2_index_start = block_size_bits + l2_bits
for i in xrange(options.num_l2caches):
@@ -132,7 +127,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
start_index_bit = l2_index_start)
l2_cntrl = L2Cache_Controller(version = i,
- cntrl_id = cntrl_count,
L2cache = l2_cache,
transitions_per_cycle=options.ports,
ruby_system = ruby_system)
@@ -140,8 +134,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
l2_cntrl_nodes.append(l2_cntrl)
- cntrl_count += 1
-
phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
assert(phys_mem_size % options.num_dirs == 0)
mem_module_size = phys_mem_size / options.num_dirs
@@ -167,22 +159,18 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
dir_size.value = mem_module_size
dir_cntrl = Directory_Controller(version = i,
- cntrl_id = cntrl_count,
directory = \
RubyDirectoryMemory(version = i,
size = dir_size,
use_map =
options.use_map),
memBuffer = mem_cntrl,
- l2_select_num_bits = l2_bits,
transitions_per_cycle = options.ports,
ruby_system = ruby_system)
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
- cntrl_count += 1
-
for i, dma_port in enumerate(dma_ports):
#
# Create the Ruby objects associated with the dma controller
@@ -191,7 +179,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
ruby_system = ruby_system)
dma_cntrl = DMA_Controller(version = i,
- cntrl_id = cntrl_count,
dma_sequencer = dma_seq,
transitions_per_cycle = options.ports,
ruby_system = ruby_system)
@@ -199,7 +186,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
- cntrl_count += 1
all_cntrls = l1_cntrl_nodes + \
l2_cntrl_nodes + \