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authorAndreas Hansson <andreas.hansson@arm.com>2012-02-14 03:41:53 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2012-02-14 03:41:53 -0500
commit00978170f3b42ea83280c1b8f4b1610f5e352394 (patch)
tree347650c916f5625cfc7c8920a3aca6b99f36f0d3 /configs/ruby/MESI_CMP_directory.py
parent0d46708dc20c438d29bd724fb7d4b54d4d2f318a (diff)
downloadgem5-00978170f3b42ea83280c1b8f4b1610f5e352394.tar.xz
MEM: Fix master/slave ports in Ruby and non-regression scripts
This patch brings the Ruby and other scripts up to date with the introduction of the master/slave ports.
Diffstat (limited to 'configs/ruby/MESI_CMP_directory.py')
-rw-r--r--configs/ruby/MESI_CMP_directory.py6
1 files changed, 3 insertions, 3 deletions
diff --git a/configs/ruby/MESI_CMP_directory.py b/configs/ruby/MESI_CMP_directory.py
index 79de421bb..4fdba3c27 100644
--- a/configs/ruby/MESI_CMP_directory.py
+++ b/configs/ruby/MESI_CMP_directory.py
@@ -103,7 +103,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
l1_cntrl.sequencer = cpu_seq
if piobus != None:
- cpu_seq.pio_port = piobus.port
+ cpu_seq.pio_port = piobus.slave
exec("system.l1_cntrl%d = l1_cntrl" % i)
@@ -180,9 +180,9 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
exec("system.dma_cntrl%d = dma_cntrl" % i)
if dma_device.type == 'MemTest':
- exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+ exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
else:
- exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
+ exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
dma_cntrl_nodes.append(dma_cntrl)
cntrl_count += 1