diff options
| author | Emilio Castillo ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) <castilloe@unican.es> | 2014-09-01 16:55:30 -0500 |
|---|---|---|
| committer | Emilio Castillo ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) <castilloe@unican.es> | 2014-09-01 16:55:30 -0500 |
| commit | 01f792a3675983411ff77b54cbee7ffee2a3d5d5 (patch) | |
| tree | 0f1d219ac9ff1d10b865d856d640884e2b177f13 /configs/ruby/MESI_Two_Level.py | |
| parent | 5efbb4442a0e8c653539e263bf87c48849280e23 (diff) | |
| download | gem5-01f792a3675983411ff77b54cbee7ffee2a3d5d5.tar.xz | |
ruby: Fixes clock domains in configuration files
This patch fixes scripts related to ruby by adding the ruby clock domain.
Now the L1 controllers and the Sequencer shares the cpu clock domain,
while the rest of the components use the ruby clock domain.
Before this patch, running simulations with the cpu clock set at 2GHz or
1GHz will output the same time results and could distort power measurements.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'configs/ruby/MESI_Two_Level.py')
| -rw-r--r-- | configs/ruby/MESI_Two_Level.py | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/configs/ruby/MESI_Two_Level.py b/configs/ruby/MESI_Two_Level.py index 845d5cf22..c70c599c7 100644 --- a/configs/ruby/MESI_Two_Level.py +++ b/configs/ruby/MESI_Two_Level.py @@ -95,12 +95,14 @@ def create_system(options, system, dma_ports, ruby_system): options.cpu_type == "detailed"), prefetcher = prefetcher, ruby_system = ruby_system, + clk_domain=system.cpu[i].clk_domain, transitions_per_cycle=options.ports, enable_prefetch = False) cpu_seq = RubySequencer(version = i, icache = l1i_cache, dcache = l1d_cache, + clk_domain=system.cpu[i].clk_domain, ruby_system = ruby_system) l1_cntrl.sequencer = cpu_seq |