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authorNilay Vaish <nilay@cs.wisc.edu>2014-02-23 19:16:16 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2014-02-23 19:16:16 -0600
commit7e27860ef4e5016f5a3c907fbe4c7858f83c8100 (patch)
tree24dddb6be57a6e5e959e91fc79eeac6a5c576703 /configs/ruby/MESI_Two_Level.py
parent5755fff99811a334874026c465ccebb9b0627230 (diff)
downloadgem5-7e27860ef4e5016f5a3c907fbe4c7858f83c8100.tar.xz
ruby: route all packets through ruby port
Currently, the interrupt controller in x86 is connected to the io bus directly. Therefore the packets between the io devices and the interrupt controller do not go through ruby. This patch changes ruby port so that these packets arrive at the ruby port first, which then routes them to their destination. Note that the patch does not make these packets go through the ruby network. That would happen in a subsequent patch.
Diffstat (limited to 'configs/ruby/MESI_Two_Level.py')
-rw-r--r--configs/ruby/MESI_Two_Level.py4
1 files changed, 3 insertions, 1 deletions
diff --git a/configs/ruby/MESI_Two_Level.py b/configs/ruby/MESI_Two_Level.py
index f7341f359..518336168 100644
--- a/configs/ruby/MESI_Two_Level.py
+++ b/configs/ruby/MESI_Two_Level.py
@@ -106,7 +106,9 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
l1_cntrl.sequencer = cpu_seq
if piobus != None:
- cpu_seq.pio_port = piobus.slave
+ cpu_seq.pio_master_port = piobus.slave
+ cpu_seq.mem_master_port = piobus.slave
+ cpu_seq.pio_slave_port = piobus.master
exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)