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authorOmar Naji <Omar.Naji@arm.com>2014-12-23 09:31:18 -0500
committerOmar Naji <Omar.Naji@arm.com>2014-12-23 09:31:18 -0500
commit381d1da79147fbe8ae62ab4886446bdd7b3c478f (patch)
tree4a6ca73e27cdedf4c53753fbdce03e8d71306cd3 /configs/ruby/MESI_Two_Level.py
parent152c02354ee53f4f4f10ac01911eb92386ef6fd2 (diff)
downloadgem5-381d1da79147fbe8ae62ab4886446bdd7b3c478f.tar.xz
mem: Add rank-wise refresh to the DRAM controller
This patch adds rank-wise refresh to the controller, as opposed to the channel-wide refresh currently in place. In essence each rank can be refreshed independently, and for this to be possible the controller is extended with a state machine per rank. Without this patch the data bus is always idle during a refresh, as all the ranks are refreshing at the same time. With the rank-wise refresh it is possible to use one rank while another one is refreshing, and thus the data bus can be kept busy. The patch introduces a Rank class to encapsulate the state per rank, and also shifts all the relevant banks, activation tracking etc to the rank. The arbitration is also updated to consider the state of the rank.
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