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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-11-06 05:41:44 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-11-06 05:41:44 -0600 |
| commit | 95a0b184314cf0171a20fb7e71c845891dc56496 (patch) | |
| tree | 00590e68aa9d66c225a8f0d08f82eca2771e461d /configs/ruby/MESI_Two_Level.py | |
| parent | 8ccfd9defa930d5c2904134d7a7286682e721db9 (diff) | |
| download | gem5-95a0b184314cf0171a20fb7e71c845891dc56496.tar.xz | |
ruby: single physical memory in fs mode
Both ruby and the system used to maintain memory copies. With the changes
carried for programmed io accesses, only one single memory is required for
fs simulations. This patch sets the copy of memory that used to reside
with the system to null, so that no space is allocated, but address checks
can still be carried out. All the memory accesses now source and sink values
to the memory maintained by ruby.
Diffstat (limited to 'configs/ruby/MESI_Two_Level.py')
| -rw-r--r-- | configs/ruby/MESI_Two_Level.py | 23 |
1 files changed, 18 insertions, 5 deletions
diff --git a/configs/ruby/MESI_Two_Level.py b/configs/ruby/MESI_Two_Level.py index 8d75fe22e..6cc4efcb9 100644 --- a/configs/ruby/MESI_Two_Level.py +++ b/configs/ruby/MESI_Two_Level.py @@ -48,7 +48,7 @@ class L2Cache(RubyCache): def define_options(parser): return -def create_system(options, system, dma_ports, ruby_system): +def create_system(options, full_system, system, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'MESI_Two_Level': fatal("This script requires the MESI_Two_Level protocol to be built.") @@ -196,7 +196,8 @@ def create_system(options, system, dma_ports, ruby_system): for i, dma_port in enumerate(dma_ports): # Create the Ruby objects associated with the dma controller dma_seq = DMASequencer(version = i, - ruby_system = ruby_system) + ruby_system = ruby_system, + slave = dma_port) dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, @@ -204,19 +205,31 @@ def create_system(options, system, dma_ports, ruby_system): ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) - exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) # Connect the dma controller to the network dma_cntrl.responseFromDir = ruby_system.network.master dma_cntrl.requestToDir = ruby_system.network.slave - all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ dma_cntrl_nodes - topology = create_topology(all_cntrls, options) + # Create the io controller and the sequencer + if full_system: + io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) + ruby_system._io_port = io_seq + io_controller = DMA_Controller(version = len(dma_ports), + dma_sequencer = io_seq, + ruby_system = ruby_system) + ruby_system.io_controller = io_controller + + # Connect the dma controller to the network + io_controller.responseFromDir = ruby_system.network.master + io_controller.requestToDir = ruby_system.network.slave + + all_cntrls = all_cntrls + [io_controller] + topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology) |