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authorNilay Vaish <nilay@cs.wisc.edu>2012-04-05 11:09:19 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2012-04-05 11:09:19 -0500
commit4f4a710457af4a9c8e72632995b55f106110ac9c (patch)
tree816cc9af7167d0d016df34768fdf701ea5d3a140 /configs/ruby/MI_example.py
parentf1a60906132fb816f80917d830b34df5e5d87ad4 (diff)
downloadgem5-4f4a710457af4a9c8e72632995b55f106110ac9c.tar.xz
Config: corrects the way Ruby attaches to the DMA ports
With recent changes to the memory system, a port cannot be assigned a peer port twice. While making use of the Ruby memory system in FS mode, DMA ports were assigned peer twice, once for the classic memory system and once for the Ruby memory system. This patch removes this double assignment of peer ports.
Diffstat (limited to 'configs/ruby/MI_example.py')
-rw-r--r--configs/ruby/MI_example.py11
1 files changed, 3 insertions, 8 deletions
diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py
index 29ed23b67..1285c4b1d 100644
--- a/configs/ruby/MI_example.py
+++ b/configs/ruby/MI_example.py
@@ -41,7 +41,7 @@ class Cache(RubyCache):
def define_options(parser):
return
-def create_system(options, system, piobus, dma_devices, ruby_system):
+def create_system(options, system, piobus, dma_ports, ruby_system):
if buildEnv['PROTOCOL'] != 'MI_example':
panic("This script requires the MI_example protocol to be built.")
@@ -135,7 +135,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
cntrl_count += 1
- for i, dma_device in enumerate(dma_devices):
+ for i, dma_port in enumerate(dma_ports):
#
# Create the Ruby objects associated with the dma controller
#
@@ -148,13 +148,8 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
ruby_system = ruby_system)
exec("system.dma_cntrl%d = dma_cntrl" % i)
- if dma_device.type == 'MemTest':
- exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
- else:
- exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
- dma_cntrl.dma_sequencer.slave = dma_device.dma
+ exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
-
cntrl_count += 1
all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes