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| author | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-03-21 21:22:20 -0700 |
|---|---|---|
| committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-03-21 21:22:20 -0700 |
| commit | 91b0c5487bcf0259eab25baef686fbef83adae1a (patch) | |
| tree | f03b7fe4632405141db83afc5357766ab466ec3b /configs/ruby/MI_example.py | |
| parent | d8e1e5abd0a560dfeb061f430bb2470a818ae5b0 (diff) | |
| download | gem5-91b0c5487bcf0259eab25baef686fbef83adae1a.tar.xz | |
ruby: Python config files now sets a unique id for each sequencer
Diffstat (limited to 'configs/ruby/MI_example.py')
| -rw-r--r-- | configs/ruby/MI_example.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py index 971a52dc8..96515971e 100644 --- a/configs/ruby/MI_example.py +++ b/configs/ruby/MI_example.py @@ -71,7 +71,8 @@ def create_system(options, phys_mem, piobus, dma_devices): # # Only one unified L1 cache exists. Can cache instructions and data. # - cpu_seq = RubySequencer(icache = cache, + cpu_seq = RubySequencer(version = i, + icache = cache, dcache = cache, physMemPort = phys_mem.port, physmem = phys_mem) |