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author | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-03-25 10:13:50 -0700 |
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committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-03-25 10:13:50 -0700 |
commit | 48b58b3332251670432db2cc7832b80eb2787bda (patch) | |
tree | 4c4adcee96e0d37e28d3032cfbe39d7737406402 /configs/ruby/MI_example.py | |
parent | 6db65b40c1acb2ea1e9f187d45430df2450cc576 (diff) | |
download | gem5-48b58b3332251670432db2cc7832b80eb2787bda.tar.xz |
ruby: fixed cache index setting
Diffstat (limited to 'configs/ruby/MI_example.py')
-rw-r--r-- | configs/ruby/MI_example.py | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py index 0e101d18f..82817d60a 100644 --- a/configs/ruby/MI_example.py +++ b/configs/ruby/MI_example.py @@ -60,6 +60,7 @@ def create_system(options, system, piobus, dma_devices): # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # + block_size_bits = int(math.log(options.cacheline_size, 2)) for i in xrange(options.num_cpus): # @@ -68,7 +69,8 @@ def create_system(options, system, piobus, dma_devices): # config parameters. # cache = Cache(size = options.l1d_size, - assoc = options.l1d_assoc) + assoc = options.l1d_assoc, + start_index_bit = block_size_bits) # # Only one unified L1 cache exists. Can cache instructions and data. |