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| author | Tiago Muck <tiago.muck@arm.com> | 2019-02-19 15:58:33 -0600 |
|---|---|---|
| committer | Tiago Mück <tiago.muck@arm.com> | 2019-05-14 22:01:12 +0000 |
| commit | 496d5ed3e1f7dad42b0c2ebe0050d84621be8f99 (patch) | |
| tree | 0ec4954d60e37d1bfe595aa6b1c7a6913a27f005 /configs/ruby/MOESI_AMD_Base.py | |
| parent | 42e55cdafdac41830839ac2584d99a8dd5e3d95e (diff) | |
| download | gem5-496d5ed3e1f7dad42b0c2ebe0050d84621be8f99.tar.xz | |
mem-ruby: Hit latencies defined by the controllers
Removed the icache/dcache hit latency parameters from the Sequencer.
They were replaced by the mandatory queue enqueue latency that is now
defined by the top-level cache controller. By default, the latency is
defined by the mandatory_queue_latency parameter. When the latency
depends on specific protocol states or on the request type, the protocol
may override the mandatoryQueueLatency function.
Change-Id: I72e57a7ea49501ef81dc7f591bef14134274647c
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18413
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'configs/ruby/MOESI_AMD_Base.py')
| -rw-r--r-- | configs/ruby/MOESI_AMD_Base.py | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/configs/ruby/MOESI_AMD_Base.py b/configs/ruby/MOESI_AMD_Base.py index 5c4bbe09c..a1faf1dfd 100644 --- a/configs/ruby/MOESI_AMD_Base.py +++ b/configs/ruby/MOESI_AMD_Base.py @@ -102,8 +102,6 @@ class CPCntrl(CorePair_Controller, CntrlBase): self.L2cache.create(options) self.sequencer = RubySequencer() - self.sequencer.icache_hit_latency = 2 - self.sequencer.dcache_hit_latency = 2 self.sequencer.version = self.seqCount() self.sequencer.icache = self.L1Icache self.sequencer.dcache = self.L1D0cache @@ -115,12 +113,13 @@ class CPCntrl(CorePair_Controller, CntrlBase): self.sequencer1.version = self.seqCount() self.sequencer1.icache = self.L1Icache self.sequencer1.dcache = self.L1D1cache - self.sequencer1.icache_hit_latency = 2 - self.sequencer1.dcache_hit_latency = 2 self.sequencer1.ruby_system = ruby_system self.sequencer1.coreid = 1 self.sequencer1.is_cpu_sequencer = True + # Defines icache/dcache hit latency + self.mandatory_queue_latency = 2 + self.issue_latency = options.cpu_to_dir_latency self.send_evictions = send_evicts(options) |