diff options
author | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-04-28 17:18:14 -0700 |
---|---|---|
committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-04-28 17:18:14 -0700 |
commit | 40bcbf42539fec83628f2ae2627238adff27f62c (patch) | |
tree | 993083e3b6e5661697261e81869bf40e17027826 /configs/ruby/MOESI_CMP_directory.py | |
parent | bc5eb596053f7f69c88f8218f20709d94b2a331c (diff) | |
download | gem5-40bcbf42539fec83628f2ae2627238adff27f62c.tar.xz |
network: convert links & switches to first class C++ SimObjects
This patch converts links and switches from second class simobjects that were
virtually ignored by the networks (both simple and Garnet) to first class
simobjects that directly correspond to c++ ojbects manipulated by the
topology and network classes. This is especially true for Garnet, where the
links and switches directly correspond to specific C++ objects.
By making this change, many aspects of the Topology class were simplified.
--HG--
rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/BasicLink.cc
rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/BasicLink.hh
rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.cc
rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.hh
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py
rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.cc
rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.hh
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py
Diffstat (limited to 'configs/ruby/MOESI_CMP_directory.py')
-rw-r--r-- | configs/ruby/MOESI_CMP_directory.py | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/configs/ruby/MOESI_CMP_directory.py b/configs/ruby/MOESI_CMP_directory.py index ff7ea0cc5..15558a62d 100644 --- a/configs/ruby/MOESI_CMP_directory.py +++ b/configs/ruby/MOESI_CMP_directory.py @@ -70,6 +70,8 @@ def create_system(options, system, piobus, dma_devices): # l2_bits = int(math.log(options.num_l2caches, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) + + cntrl_count = 0 for i in xrange(options.num_cpus): # @@ -92,6 +94,7 @@ def create_system(options, system, piobus, dma_devices): cpu_seq.pio_port = piobus.port l1_cntrl = L1Cache_Controller(version = i, + cntrl_id = cntrl_count, sequencer = cpu_seq, L1IcacheMemory = l1i_cache, L1DcacheMemory = l1d_cache, @@ -104,6 +107,8 @@ def create_system(options, system, piobus, dma_devices): cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) + cntrl_count += 1 + l2_index_start = block_size_bits + l2_bits for i in xrange(options.num_l2caches): @@ -115,10 +120,13 @@ def create_system(options, system, piobus, dma_devices): start_index_bit = l2_index_start) l2_cntrl = L2Cache_Controller(version = i, + cntrl_id = cntrl_count, L2cacheMemory = l2_cache) exec("system.l2_cntrl%d = l2_cntrl" % i) l2_cntrl_nodes.append(l2_cntrl) + + cntrl_count += 1 phys_mem_size = long(system.physmem.range.second) - \ long(system.physmem.range.first) + 1 @@ -135,6 +143,7 @@ def create_system(options, system, piobus, dma_devices): dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, + cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory(version = i, size = \ @@ -144,6 +153,8 @@ def create_system(options, system, piobus, dma_devices): exec("system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) + cntrl_count += 1 + for i, dma_device in enumerate(dma_devices): # # Create the Ruby objects associated with the dma controller @@ -153,6 +164,7 @@ def create_system(options, system, piobus, dma_devices): physmem = system.physmem) dma_cntrl = DMA_Controller(version = i, + cntrl_id = cntrl_count, dma_sequencer = dma_seq) exec("system.dma_cntrl%d = dma_cntrl" % i) @@ -162,6 +174,8 @@ def create_system(options, system, piobus, dma_devices): exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i) dma_cntrl_nodes.append(dma_cntrl) + cntrl_count += 1 + all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ |