summaryrefslogtreecommitdiff
path: root/configs/ruby/MOESI_CMP_directory.py
diff options
context:
space:
mode:
authorNilay Vaish <nilay@cs.wisc.edu>2012-01-23 11:07:14 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2012-01-23 11:07:14 -0600
commit63563c9df2eca46231768a448e981e8bb7856655 (patch)
treed45aaa1decb0d9dba3ccd01d7ecb31804d85f1f8 /configs/ruby/MOESI_CMP_directory.py
parent9481d05b8aea0faf336f604f3e18b451d5197c12 (diff)
downloadgem5-63563c9df2eca46231768a448e981e8bb7856655.tar.xz
O3, Ruby: Forward invalidations from Ruby to O3 CPU
This patch implements the functionality for forwarding invalidations and replacements from the L1 cache of the Ruby memory system to the O3 CPU. The implementation adds a list of ports to RubyPort. Whenever a replacement or an invalidation is performed, the L1 cache forwards this to all the ports, which is the LSQ in case of the O3 CPU.
Diffstat (limited to 'configs/ruby/MOESI_CMP_directory.py')
-rw-r--r--configs/ruby/MOESI_CMP_directory.py2
1 files changed, 2 insertions, 0 deletions
diff --git a/configs/ruby/MOESI_CMP_directory.py b/configs/ruby/MOESI_CMP_directory.py
index e3bc9ae85..f6baa4026 100644
--- a/configs/ruby/MOESI_CMP_directory.py
+++ b/configs/ruby/MOESI_CMP_directory.py
@@ -89,6 +89,8 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
L1IcacheMemory = l1i_cache,
L1DcacheMemory = l1d_cache,
l2_select_num_bits = l2_bits,
+ send_evictions = (
+ options.cpu_type == "detailed"),
ruby_system = ruby_system)
cpu_seq = RubySequencer(version = i,