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authorMalek Musleh <malek.musleh@gmail.com>2013-01-14 10:05:14 -0600
committerMalek Musleh <malek.musleh@gmail.com>2013-01-14 10:05:14 -0600
commit3137557cadf0635c7593a4fb6c37d903d3048c13 (patch)
tree178d320ec2c2055dbec418a5531e3464336f571c /configs/ruby/MOESI_hammer.py
parent1abf950f3c4ce407c39cb0c86c834b7048181c07 (diff)
downloadgem5-3137557cadf0635c7593a4fb6c37d903d3048c13.tar.xz
config: move ruby objects under ruby_system in obj hierarchy
This patch moves the contollers to be children of the ruby_system instead of 'system' under the python object hierarchy. This is so that these objects can inherit some of the ruby_system's parameter values without resorting to calling a global system pointer during run-time. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'configs/ruby/MOESI_hammer.py')
-rw-r--r--configs/ruby/MOESI_hammer.py8
1 files changed, 4 insertions, 4 deletions
diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index d0f38d922..1919386c0 100644
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -122,7 +122,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
if options.recycle_latency:
l1_cntrl.recycle_latency = options.recycle_latency
- exec("system.l1_cntrl%d = l1_cntrl" % i)
+ exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
#
@@ -192,7 +192,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
if options.recycle_latency:
dir_cntrl.recycle_latency = options.recycle_latency
- exec("system.dir_cntrl%d = dir_cntrl" % i)
+ exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
cntrl_count += 1
@@ -209,8 +209,8 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
dma_sequencer = dma_seq,
ruby_system = ruby_system)
- exec("system.dma_cntrl%d = dma_cntrl" % i)
- exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
+ exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
+ exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
if options.recycle_latency: