config: Improve ruby simobject names

This patch attaches ruby objects to the system before the topology is
created so that their simobject names read their meaningful variable
names instead of their topology name.

1 files changed, 17 insertions, 10 deletions

diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index 705b569ac..45b08a288 100644
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -46,7 +46,7 @@ class L2Cache(RubyCache):
 def define_options(parser):
     return
 
-def create_system(options, phys_mem, piobus, dma_devices):
+def create_system(options, system, piobus, dma_devices):
     
     if buildEnv['PROTOCOL'] != 'MOESI_hammer':
         panic("This script requires the MOESI_hammer protocol to be built.")
@@ -81,8 +81,8 @@ def create_system(options, phys_mem, piobus, dma_devices):
         cpu_seq = RubySequencer(version = i,
                                 icache = l1i_cache,
                                 dcache = l1d_cache,
-                                physMemPort = phys_mem.port,
-                                physmem = phys_mem)
+                                physMemPort = system.physmem.port,
+                                physmem = system.physmem)
 
         if piobus != None:
             cpu_seq.pio_port = piobus.port
@@ -92,13 +92,16 @@ def create_system(options, phys_mem, piobus, dma_devices):
                                       L1IcacheMemory = l1i_cache,
                                       L1DcacheMemory = l1d_cache,
                                       L2cacheMemory = l2_cache)
+
+        exec("system.l1_cntrl%d = l1_cntrl" % i)
         #
         # Add controllers and sequencers to the appropriate lists
         #
         cpu_sequencers.append(cpu_seq)
         l1_cntrl_nodes.append(l1_cntrl)
 
-    phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
+    phys_mem_size = long(system.physmem.range.second) - \
+                      long(system.physmem.range.first) + 1
     mem_module_size = phys_mem_size / options.num_dirs
 
     for i in xrange(options.num_dirs):
@@ -113,12 +116,15 @@ def create_system(options, phys_mem, piobus, dma_devices):
 
         dir_cntrl = Directory_Controller(version = i,
                                          directory = \
-                                         RubyDirectoryMemory(version = i,
-                                               size = dir_size,
-                                               use_map = options.use_map,
-                                               map_levels = options.map_levels),
+                                         RubyDirectoryMemory( \
+                                                    version = i,
+                                                    size = dir_size,
+                                                    use_map = options.use_map,
+                                                    map_levels = \
+                                                    options.map_levels),
                                          memBuffer = mem_cntrl)
 
+        exec("system.dir_cntrl%d = dir_cntrl" % i)
         dir_cntrl_nodes.append(dir_cntrl)
 
     for i, dma_device in enumerate(dma_devices):
@@ -126,12 +132,13 @@ def create_system(options, phys_mem, piobus, dma_devices):
         # Create the Ruby objects associated with the dma controller
         #
         dma_seq = DMASequencer(version = i,
-                               physMemPort = phys_mem.port,
-                               physmem = phys_mem)
+                               physMemPort = system.physmem.port,
+                               physmem = system.physmem)
         
         dma_cntrl = DMA_Controller(version = i,
                                    dma_sequencer = dma_seq)
 
+        exec("system.dma_cntrl%d = dma_cntrl" % i)
         dma_cntrl.dma_sequencer.port = dma_device.dma
         dma_cntrl_nodes.append(dma_cntrl)