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authorBrad Beckmann <Brad.Beckmann@amd.com>2015-07-20 09:15:18 -0500
committerBrad Beckmann <Brad.Beckmann@amd.com>2015-07-20 09:15:18 -0500
commit173a7869219534de5053889a84e1006281ec7645 (patch)
tree0cbd44d0669204d4fb3a551e98b1b668f8e6bee4 /configs/ruby/MOESI_hammer.py
parent4e6241007c514c3f90e9aeebf7cfd92853e45850 (diff)
downloadgem5-173a7869219534de5053889a84e1006281ec7645.tar.xz
ruby: more flexible ruby tester support
This patch allows the ruby random tester to use ruby ports that may only support instr or data requests. This patch is similar to a previous changeset (8932:1b2c17565ac8) that was unfortunately broken by subsequent changesets. This current patch implements the support in a more straight-forward way. Since retries are now tested when running the ruby random tester, this patch splits up the retry and drain check behavior so that RubyPort children, such as the GPUCoalescer, can perform those operations correctly without having to duplicate code. Finally, the patch also includes better DPRINTFs for debugging the tester.
Diffstat (limited to 'configs/ruby/MOESI_hammer.py')
-rw-r--r--configs/ruby/MOESI_hammer.py40
1 files changed, 24 insertions, 16 deletions
diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index 0860fb682..6a1cfd70b 100644
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -89,22 +89,30 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
assoc = options.l2_assoc,
start_index_bit = block_size_bits)
- l1_cntrl = L1Cache_Controller(version = i,
- L1Icache = l1i_cache,
- L1Dcache = l1d_cache,
- L2cache = l2_cache,
- no_mig_atomic = not \
- options.allow_atomic_migration,
- send_evictions = send_evicts(options),
- transitions_per_cycle = options.ports,
- clk_domain=system.cpu[i].clk_domain,
- ruby_system = ruby_system)
-
- cpu_seq = RubySequencer(version = i,
- icache = l1i_cache,
- dcache = l1d_cache,
- clk_domain=system.cpu[i].clk_domain,
- ruby_system = ruby_system)
+ # the ruby random tester reuses num_cpus to specify the
+ # number of cpu ports connected to the tester object, which
+ # is stored in system.cpu. because there is only ever one
+ # tester object, num_cpus is not necessarily equal to the
+ # size of system.cpu; therefore if len(system.cpu) == 1
+ # we use system.cpu[0] to set the clk_domain, thereby ensuring
+ # we don't index off the end of the cpu list.
+ if len(system.cpu) == 1:
+ clk_domain = system.cpu[0].clk_domain
+ else:
+ clk_domain = system.cpu[i].clk_domain
+
+ l1_cntrl = L1Cache_Controller(version=i, L1Icache=l1i_cache,
+ L1Dcache=l1d_cache, L2cache=l2_cache,
+ no_mig_atomic=not \
+ options.allow_atomic_migration,
+ send_evictions=send_evicts(options),
+ transitions_per_cycle=options.ports,
+ clk_domain=clk_domain,
+ ruby_system=ruby_system)
+
+ cpu_seq = RubySequencer(version=i, icache=l1i_cache,
+ dcache=l1d_cache,clk_domain=clk_domain,
+ ruby_system=ruby_system)
l1_cntrl.sequencer = cpu_seq
if options.recycle_latency: