diff options
author | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-08-20 11:41:35 -0700 |
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committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-08-20 11:41:35 -0700 |
commit | 7816d0d12b87ace096dba5282be1f054c4615c95 (patch) | |
tree | 08cb7748ef840c1d3648cf7ff1ab8cf24d6ab010 /configs/ruby/protocols/MI_example.py | |
parent | e0754c0f6c046147926088c4b356d2a9c199bce2 (diff) | |
download | gem5-7816d0d12b87ace096dba5282be1f054c4615c95.tar.xz |
config: moved python protocol config files
Moved the python protocol config files back to their original location to avoid
addToPath calls.
--HG--
rename : configs/ruby/protocols/MESI_CMP_directory.py => configs/ruby/MESI_CMP_directory.py
rename : configs/ruby/protocols/MI_example.py => configs/ruby/MI_example.py
rename : configs/ruby/protocols/MOESI_CMP_directory.py => configs/ruby/MOESI_CMP_directory.py
rename : configs/ruby/protocols/MOESI_CMP_token.py => configs/ruby/MOESI_CMP_token.py
rename : configs/ruby/protocols/MOESI_hammer.py => configs/ruby/MOESI_hammer.py
Diffstat (limited to 'configs/ruby/protocols/MI_example.py')
-rw-r--r-- | configs/ruby/protocols/MI_example.py | 131 |
1 files changed, 0 insertions, 131 deletions
diff --git a/configs/ruby/protocols/MI_example.py b/configs/ruby/protocols/MI_example.py deleted file mode 100644 index f4033caeb..000000000 --- a/configs/ruby/protocols/MI_example.py +++ /dev/null @@ -1,131 +0,0 @@ -# Copyright (c) 2006-2007 The Regents of The University of Michigan -# Copyright (c) 2009 Advanced Micro Devices, Inc. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Brad Beckmann - -import m5 -from m5.objects import * -from m5.defines import buildEnv -from m5.util import addToPath - -# -# Note: the cache latency is only used by the sequencer on fast path hits -# -class Cache(RubyCache): - latency = 3 - -def create_system(options, phys_mem, piobus, dma_devices): - - if buildEnv['PROTOCOL'] != 'MI_example': - panic("This script requires the MI_example protocol to be built.") - - cpu_sequencers = [] - - # - # The ruby network creation expects the list of nodes in the system to be - # consistent with the NetDest list. Therefore the l1 controller nodes must be - # listed before the directory nodes and directory nodes before dma nodes, etc. - # - l1_cntrl_nodes = [] - dir_cntrl_nodes = [] - dma_cntrl_nodes = [] - - # - # Must create the individual controllers before the network to ensure the - # controller constructors are called before the network constructor - # - - for i in xrange(options.num_cpus): - # - # First create the Ruby objects associated with this cpu - # Only one cache exists for this protocol, so by default use the L1D - # config parameters. - # - cache = Cache(size = options.l1d_size, - assoc = options.l1d_assoc) - - # - # Only one unified L1 cache exists. Can cache instructions and data. - # - cpu_seq = RubySequencer(version = i, - icache = cache, - dcache = cache, - physMemPort = phys_mem.port, - physmem = phys_mem) - - if piobus != None: - cpu_seq.pio_port = piobus.port - - l1_cntrl = L1Cache_Controller(version = i, - sequencer = cpu_seq, - cacheMemory = cache) - # - # Add controllers and sequencers to the appropriate lists - # - cpu_sequencers.append(cpu_seq) - l1_cntrl_nodes.append(l1_cntrl) - - phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1 - mem_module_size = phys_mem_size / options.num_dirs - - for i in xrange(options.num_dirs): - # - # Create the Ruby objects associated with the directory controller - # - - mem_cntrl = RubyMemoryControl(version = i) - - dir_size = MemorySize('0B') - dir_size.value = mem_module_size - - dir_cntrl = Directory_Controller(version = i, - directory = \ - RubyDirectoryMemory(version = i, - size = dir_size, - use_map = options.use_map, - map_levels = options.map_levels), - memBuffer = mem_cntrl) - - dir_cntrl_nodes.append(dir_cntrl) - - for i, dma_device in enumerate(dma_devices): - # - # Create the Ruby objects associated with the dma controller - # - dma_seq = DMASequencer(version = i, - physMemPort = phys_mem.port, - physmem = phys_mem) - - dma_cntrl = DMA_Controller(version = i, - dma_sequencer = dma_seq) - - dma_cntrl.dma_sequencer.port = dma_device.dma - dma_cntrl_nodes.append(dma_cntrl) - - all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes - - return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) |