network: convert links & switches to first class C++ SimObjects

This patch converts links and switches from second class simobjects that were
virtually ignored by the networks (both simple and Garnet) to first class
simobjects that directly correspond to c++ ojbects manipulated by the
topology and network classes.  This is especially true for Garnet, where the
links and switches directly correspond to specific C++ objects.

By making this change, many aspects of the Topology class were simplified.

--HG--
rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/BasicLink.cc
rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/BasicLink.hh
rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.cc
rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.hh
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py
rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.cc
rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.hh
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py

7 files changed, 97 insertions, 9 deletions

diff --git a/configs/ruby/MESI_CMP_directory.py b/configs/ruby/MESI_CMP_directory.py
index 2f7faab52..4bd969be5 100644
--- a/configs/ruby/MESI_CMP_directory.py
+++ b/configs/ruby/MESI_CMP_directory.py
@@ -71,6 +71,8 @@ def create_system(options, system, piobus, dma_devices):
     l2_bits = int(math.log(options.num_l2caches, 2))
     block_size_bits = int(math.log(options.cacheline_size, 2))
     
+    cntrl_count = 0
+    
     for i in xrange(options.num_cpus):
         #
         # First create the Ruby objects associated with this cpu
@@ -92,6 +94,7 @@ def create_system(options, system, piobus, dma_devices):
             cpu_seq.pio_port = piobus.port
 
         l1_cntrl = L1Cache_Controller(version = i,
+                                      cntrl_id = cntrl_count,
                                       sequencer = cpu_seq,
                                       L1IcacheMemory = l1i_cache,
                                       L1DcacheMemory = l1d_cache,
@@ -104,6 +107,8 @@ def create_system(options, system, piobus, dma_devices):
         #
         cpu_sequencers.append(cpu_seq)
         l1_cntrl_nodes.append(l1_cntrl)
+        
+        cntrl_count += 1
 
     l2_index_start = block_size_bits + l2_bits
 
@@ -116,11 +121,14 @@ def create_system(options, system, piobus, dma_devices):
                            start_index_bit = l2_index_start)
 
         l2_cntrl = L2Cache_Controller(version = i,
+                                      cntrl_id = cntrl_count,
                                       L2cacheMemory = l2_cache)
         
         exec("system.l2_cntrl%d = l2_cntrl" % i)
         l2_cntrl_nodes.append(l2_cntrl)
         
+        cntrl_count += 1
+        
     phys_mem_size = long(system.physmem.range.second) - \
                       long(system.physmem.range.first) + 1
     mem_module_size = phys_mem_size / options.num_dirs
@@ -136,6 +144,7 @@ def create_system(options, system, piobus, dma_devices):
         dir_size.value = mem_module_size
 
         dir_cntrl = Directory_Controller(version = i,
+                                         cntrl_id = cntrl_count,
                                          directory = \
                                          RubyDirectoryMemory(version = i,
                                                              size = \
@@ -145,6 +154,8 @@ def create_system(options, system, piobus, dma_devices):
         exec("system.dir_cntrl%d = dir_cntrl" % i)
         dir_cntrl_nodes.append(dir_cntrl)
 
+        cntrl_count += 1
+
     for i, dma_device in enumerate(dma_devices):
         #
         # Create the Ruby objects associated with the dma controller
@@ -154,6 +165,7 @@ def create_system(options, system, piobus, dma_devices):
                                physmem = system.physmem)
         
         dma_cntrl = DMA_Controller(version = i,
+                                   cntrl_id = cntrl_count,
                                    dma_sequencer = dma_seq)
 
         exec("system.dma_cntrl%d = dma_cntrl" % i)
@@ -163,6 +175,8 @@ def create_system(options, system, piobus, dma_devices):
             exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
         dma_cntrl_nodes.append(dma_cntrl)
 
+        cntrl_count += 1
+
     all_cntrls = l1_cntrl_nodes + \
                  l2_cntrl_nodes + \
                  dir_cntrl_nodes + \
diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py
index 062748eef..5f5703d4e 100644
--- a/configs/ruby/MI_example.py
+++ b/configs/ruby/MI_example.py
@@ -62,6 +62,8 @@ def create_system(options, system, piobus, dma_devices):
     # controller constructors are called before the network constructor
     #
     block_size_bits = int(math.log(options.cacheline_size, 2))
+
+    cntrl_count = 0
     
     for i in xrange(options.num_cpus):
         #
@@ -86,6 +88,7 @@ def create_system(options, system, piobus, dma_devices):
             cpu_seq.pio_port = piobus.port
 
         l1_cntrl = L1Cache_Controller(version = i,
+                                      cntrl_id = cntrl_count,
                                       sequencer = cpu_seq,
                                       cacheMemory = cache)
 
@@ -96,6 +99,8 @@ def create_system(options, system, piobus, dma_devices):
         cpu_sequencers.append(cpu_seq)
         l1_cntrl_nodes.append(l1_cntrl)
 
+        cntrl_count += 1
+
     phys_mem_size = long(system.physmem.range.second) - \
                       long(system.physmem.range.first) + 1
     mem_module_size = phys_mem_size / options.num_dirs
@@ -111,6 +116,7 @@ def create_system(options, system, piobus, dma_devices):
         dir_size.value = mem_module_size
 
         dir_cntrl = Directory_Controller(version = i,
+                                         cntrl_id = cntrl_count,
                                          directory = \
                                          RubyDirectoryMemory( \
                                                     version = i,
@@ -123,6 +129,8 @@ def create_system(options, system, piobus, dma_devices):
         exec("system.dir_cntrl%d = dir_cntrl" % i)
         dir_cntrl_nodes.append(dir_cntrl)
 
+        cntrl_count += 1
+
     for i, dma_device in enumerate(dma_devices):
         #
         # Create the Ruby objects associated with the dma controller
@@ -132,6 +140,7 @@ def create_system(options, system, piobus, dma_devices):
                                physmem = system.physmem)
         
         dma_cntrl = DMA_Controller(version = i,
+                                   cntrl_id = cntrl_count,
                                    dma_sequencer = dma_seq)
 
         exec("system.dma_cntrl%d = dma_cntrl" % i)
@@ -142,6 +151,8 @@ def create_system(options, system, piobus, dma_devices):
         dma_cntrl.dma_sequencer.port = dma_device.dma
         dma_cntrl_nodes.append(dma_cntrl)
 
+        cntrl_count += 1
+
     all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
 
     return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
diff --git a/configs/ruby/MOESI_CMP_directory.py b/configs/ruby/MOESI_CMP_directory.py
index ff7ea0cc5..15558a62d 100644
--- a/configs/ruby/MOESI_CMP_directory.py
+++ b/configs/ruby/MOESI_CMP_directory.py
@@ -70,6 +70,8 @@ def create_system(options, system, piobus, dma_devices):
     #
     l2_bits = int(math.log(options.num_l2caches, 2))
     block_size_bits = int(math.log(options.cacheline_size, 2))
+
+    cntrl_count = 0
     
     for i in xrange(options.num_cpus):
         #
@@ -92,6 +94,7 @@ def create_system(options, system, piobus, dma_devices):
             cpu_seq.pio_port = piobus.port
 
         l1_cntrl = L1Cache_Controller(version = i,
+                                      cntrl_id = cntrl_count,
                                       sequencer = cpu_seq,
                                       L1IcacheMemory = l1i_cache,
                                       L1DcacheMemory = l1d_cache,
@@ -104,6 +107,8 @@ def create_system(options, system, piobus, dma_devices):
         cpu_sequencers.append(cpu_seq)
         l1_cntrl_nodes.append(l1_cntrl)
 
+        cntrl_count += 1
+
     l2_index_start = block_size_bits + l2_bits
 
     for i in xrange(options.num_l2caches):
@@ -115,10 +120,13 @@ def create_system(options, system, piobus, dma_devices):
                            start_index_bit = l2_index_start)
 
         l2_cntrl = L2Cache_Controller(version = i,
+                                      cntrl_id = cntrl_count,
                                       L2cacheMemory = l2_cache)
         
         exec("system.l2_cntrl%d = l2_cntrl" % i)
         l2_cntrl_nodes.append(l2_cntrl)
+
+        cntrl_count += 1
         
     phys_mem_size = long(system.physmem.range.second) - \
                       long(system.physmem.range.first) + 1
@@ -135,6 +143,7 @@ def create_system(options, system, piobus, dma_devices):
         dir_size.value = mem_module_size
 
         dir_cntrl = Directory_Controller(version = i,
+                                         cntrl_id = cntrl_count,
                                          directory = \
                                          RubyDirectoryMemory(version = i,
                                                              size = \
@@ -144,6 +153,8 @@ def create_system(options, system, piobus, dma_devices):
         exec("system.dir_cntrl%d = dir_cntrl" % i)
         dir_cntrl_nodes.append(dir_cntrl)
 
+        cntrl_count += 1
+
     for i, dma_device in enumerate(dma_devices):
         #
         # Create the Ruby objects associated with the dma controller
@@ -153,6 +164,7 @@ def create_system(options, system, piobus, dma_devices):
                                physmem = system.physmem)
         
         dma_cntrl = DMA_Controller(version = i,
+                                   cntrl_id = cntrl_count,
                                    dma_sequencer = dma_seq)
 
         exec("system.dma_cntrl%d = dma_cntrl" % i)
@@ -162,6 +174,8 @@ def create_system(options, system, piobus, dma_devices):
             exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
         dma_cntrl_nodes.append(dma_cntrl)
 
+        cntrl_count += 1
+
     all_cntrls = l1_cntrl_nodes + \
                  l2_cntrl_nodes + \
                  dir_cntrl_nodes + \
diff --git a/configs/ruby/MOESI_CMP_token.py b/configs/ruby/MOESI_CMP_token.py
index 72721058b..5b6e21f33 100644
--- a/configs/ruby/MOESI_CMP_token.py
+++ b/configs/ruby/MOESI_CMP_token.py
@@ -84,6 +84,8 @@ def create_system(options, system, piobus, dma_devices):
     l2_bits = int(math.log(options.num_l2caches, 2))
     block_size_bits = int(math.log(options.cacheline_size, 2))
     
+    cntrl_count = 0
+
     for i in xrange(options.num_cpus):
         #
         # First create the Ruby objects associated with this cpu
@@ -105,6 +107,7 @@ def create_system(options, system, piobus, dma_devices):
             cpu_seq.pio_port = piobus.port
 
         l1_cntrl = L1Cache_Controller(version = i,
+                                      cntrl_id = cntrl_count,
                                       sequencer = cpu_seq,
                                       L1IcacheMemory = l1i_cache,
                                       L1DcacheMemory = l1d_cache,
@@ -126,6 +129,8 @@ def create_system(options, system, piobus, dma_devices):
         cpu_sequencers.append(cpu_seq)
         l1_cntrl_nodes.append(l1_cntrl)
 
+        cntrl_count += 1
+
     l2_index_start = block_size_bits + l2_bits
 
     for i in xrange(options.num_l2caches):
@@ -137,11 +142,14 @@ def create_system(options, system, piobus, dma_devices):
                            start_index_bit = l2_index_start)
 
         l2_cntrl = L2Cache_Controller(version = i,
+                                      cntrl_id = cntrl_count,
                                       L2cacheMemory = l2_cache,
                                       N_tokens = n_tokens)
         
         exec("system.l2_cntrl%d = l2_cntrl" % i)
         l2_cntrl_nodes.append(l2_cntrl)
+
+        cntrl_count += 1
         
     phys_mem_size = long(system.physmem.range.second) - \
                       long(system.physmem.range.first) + 1
@@ -158,6 +166,7 @@ def create_system(options, system, piobus, dma_devices):
         dir_size.value = mem_module_size
 
         dir_cntrl = Directory_Controller(version = i,
+                                         cntrl_id = cntrl_count,
                                          directory = \
                                          RubyDirectoryMemory(version = i,
                                                              size = \
@@ -168,6 +177,8 @@ def create_system(options, system, piobus, dma_devices):
         exec("system.dir_cntrl%d = dir_cntrl" % i)
         dir_cntrl_nodes.append(dir_cntrl)
 
+        cntrl_count += 1
+
     for i, dma_device in enumerate(dma_devices):
         #
         # Create the Ruby objects associated with the dma controller
@@ -177,6 +188,7 @@ def create_system(options, system, piobus, dma_devices):
                                physmem = system.physmem)
         
         dma_cntrl = DMA_Controller(version = i,
+                                   cntrl_id = cntrl_count,
                                    dma_sequencer = dma_seq)
 
         exec("system.dma_cntrl%d = dma_cntrl" % i)
@@ -186,6 +198,8 @@ def create_system(options, system, piobus, dma_devices):
             exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
         dma_cntrl_nodes.append(dma_cntrl)
 
+        cntrl_count += 1
+
     all_cntrls = l1_cntrl_nodes + \
                  l2_cntrl_nodes + \
                  dir_cntrl_nodes + \
diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index 3804a58b1..4a0391264 100644
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -79,6 +79,8 @@ def create_system(options, system, piobus, dma_devices):
     # controller constructors are called before the network constructor
     #
     block_size_bits = int(math.log(options.cacheline_size, 2))
+
+    cntrl_count = 0
     
     for i in xrange(options.num_cpus):
         #
@@ -104,6 +106,7 @@ def create_system(options, system, piobus, dma_devices):
             cpu_seq.pio_port = piobus.port
 
         l1_cntrl = L1Cache_Controller(version = i,
+                                      cntrl_id = cntrl_count,
                                       sequencer = cpu_seq,
                                       L1IcacheMemory = l1i_cache,
                                       L1DcacheMemory = l1d_cache,
@@ -121,6 +124,8 @@ def create_system(options, system, piobus, dma_devices):
         cpu_sequencers.append(cpu_seq)
         l1_cntrl_nodes.append(l1_cntrl)
 
+        cntrl_count += 1
+
     phys_mem_size = long(system.physmem.range.second) - \
                       long(system.physmem.range.first) + 1
     mem_module_size = phys_mem_size / options.num_dirs
@@ -162,6 +167,7 @@ def create_system(options, system, piobus, dma_devices):
                          start_index_bit = pf_start_bit)
 
         dir_cntrl = Directory_Controller(version = i,
+                                         cntrl_id = cntrl_count,
                                          directory = \
                                          RubyDirectoryMemory( \
                                                     version = i,
@@ -182,6 +188,8 @@ def create_system(options, system, piobus, dma_devices):
         exec("system.dir_cntrl%d = dir_cntrl" % i)
         dir_cntrl_nodes.append(dir_cntrl)
 
+        cntrl_count += 1
+
     for i, dma_device in enumerate(dma_devices):
         #
         # Create the Ruby objects associated with the dma controller
@@ -191,6 +199,7 @@ def create_system(options, system, piobus, dma_devices):
                                physmem = system.physmem)
         
         dma_cntrl = DMA_Controller(version = i,
+                                   cntrl_id = cntrl_count,
                                    dma_sequencer = dma_seq)
 
         exec("system.dma_cntrl%d = dma_cntrl" % i)
@@ -203,6 +212,8 @@ def create_system(options, system, piobus, dma_devices):
         if options.recycle_latency:
             dma_cntrl.recycle_latency = options.recycle_latency
 
+        cntrl_count += 1
+
     all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
 
     return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
diff --git a/configs/ruby/Network_test.py b/configs/ruby/Network_test.py
index fe1559f53..75ec9099e 100644
--- a/configs/ruby/Network_test.py
+++ b/configs/ruby/Network_test.py
@@ -69,6 +69,8 @@ def create_system(options, system, piobus, dma_devices):
     # controller constructors are called before the network constructor
     #
 
+    cntrl_count = 0
+
     for i in xrange(options.num_cpus):
         #
         # First create the Ruby objects associated with this cpu
@@ -91,6 +93,7 @@ def create_system(options, system, piobus, dma_devices):
             cpu_seq.pio_port = piobus.port
 
         l1_cntrl = L1Cache_Controller(version = i,
+                                      cntrl_id = cntrl_count,
                                       sequencer = cpu_seq,
                                       cacheMemory = cache)
 
@@ -101,6 +104,8 @@ def create_system(options, system, piobus, dma_devices):
         cpu_sequencers.append(cpu_seq)
         l1_cntrl_nodes.append(l1_cntrl)
 
+        cntrl_count += 1
+
     phys_mem_size = long(system.physmem.range.second) - \
                       long(system.physmem.range.first) + 1
     mem_module_size = phys_mem_size / options.num_dirs
@@ -116,6 +121,7 @@ def create_system(options, system, piobus, dma_devices):
         dir_size.value = mem_module_size
 
         dir_cntrl = Directory_Controller(version = i,
+                                         cntrl_id = cntrl_count,
                                          directory = \
                                          RubyDirectoryMemory(version = i,
                                                              size = dir_size),
@@ -124,6 +130,8 @@ def create_system(options, system, piobus, dma_devices):
         exec("system.dir_cntrl%d = dir_cntrl" % i)
         dir_cntrl_nodes.append(dir_cntrl)
 
+        cntrl_count += 1
+
     all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes
 
     return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index e5d3c4a7c..7f32829d6 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -71,25 +71,41 @@ def create_system(options, system, piobus = None, dma_devices = []):
     except:
         print "Error: could not create sytem for ruby protocol %s" % protocol
         raise
-        
+
+    #
+    # Set the network classes based on the command line options
+    #
+    if options.garnet_network == "fixed":
+        class NetworkClass(GarnetNetwork_d): pass
+        class IntLinkClass(GarnetIntLink_d): pass
+        class ExtLinkClass(GarnetExtLink_d): pass
+        class RouterClass(GarnetRouter_d): pass
+    elif options.garnet_network == "flexible":
+        class NetworkClass(GarnetNetwork): pass
+        class IntLinkClass(GarnetIntLink): pass
+        class ExtLinkClass(GarnetExtLink): pass
+        class RouterClass(GarnetRouter): pass
+    else:
+        class NetworkClass(SimpleNetwork): pass
+        class IntLinkClass(BasicIntLink): pass
+        class ExtLinkClass(BasicExtLink): pass
+        class RouterClass(BasicRouter): pass
+    
     #
     # Important: the topology must be created before the network and after the
     # controllers.
     #
     exec "import %s" % options.topology
     try:
-        net_topology = eval("%s.makeTopology(all_cntrls, options)" \
+        net_topology = eval("%s.makeTopology(all_cntrls, options, \
+                                             IntLinkClass, ExtLinkClass, \
+                                             RouterClass)" \
                             % options.topology)
     except:
         print "Error: could not create topology %s" % options.topology
         raise
-        
-    if options.garnet_network == "fixed":
-        network = GarnetNetwork_d(topology = net_topology)
-    elif options.garnet_network == "flexible":
-        network = GarnetNetwork(topology = net_topology)
-    else:
-        network = SimpleNetwork(topology = net_topology)
+
+    network = NetworkClass(topology = net_topology)
 
     #
     # Loop through the directory controlers.