MEM: Fix master/slave ports in Ruby and non-regression scripts

This patch brings the Ruby and other scripts up to date with the
introduction of the master/slave ports.

6 files changed, 17 insertions, 17 deletions

diff --git a/configs/ruby/MESI_CMP_directory.py b/configs/ruby/MESI_CMP_directory.py
index 79de421bb..4fdba3c27 100644
--- a/configs/ruby/MESI_CMP_directory.py
+++ b/configs/ruby/MESI_CMP_directory.py
@@ -103,7 +103,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.port
+            cpu_seq.pio_port = piobus.slave
 
         exec("system.l1_cntrl%d = l1_cntrl" % i)
         
@@ -180,9 +180,9 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
 
         exec("system.dma_cntrl%d = dma_cntrl" % i)
         if dma_device.type == 'MemTest':
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
         else:
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
         dma_cntrl_nodes.append(dma_cntrl)
 
         cntrl_count += 1
diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py
index 13f4c9c80..851001b6f 100644
--- a/configs/ruby/MI_example.py
+++ b/configs/ruby/MI_example.py
@@ -95,7 +95,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.port
+            cpu_seq.pio_port = piobus.slave
 
         exec("system.l1_cntrl%d = l1_cntrl" % i)
         #
@@ -153,10 +153,10 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
 
         exec("system.dma_cntrl%d = dma_cntrl" % i)
         if dma_device.type == 'MemTest':
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
         else:
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
-        dma_cntrl.dma_sequencer.port = dma_device.dma
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
+        dma_cntrl.dma_sequencer.slave = dma_device.dma
         dma_cntrl_nodes.append(dma_cntrl)
 
         cntrl_count += 1
diff --git a/configs/ruby/MOESI_CMP_directory.py b/configs/ruby/MOESI_CMP_directory.py
index f6baa4026..ac582e4e6 100644
--- a/configs/ruby/MOESI_CMP_directory.py
+++ b/configs/ruby/MOESI_CMP_directory.py
@@ -103,7 +103,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.port
+            cpu_seq.pio_port = piobus.slave
 
         exec("system.l1_cntrl%d = l1_cntrl" % i)
         #
@@ -177,9 +177,9 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
 
         exec("system.dma_cntrl%d = dma_cntrl" % i)
         if dma_device.type == 'MemTest':
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
         else:
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
         dma_cntrl_nodes.append(dma_cntrl)
 
         cntrl_count += 1
diff --git a/configs/ruby/MOESI_CMP_token.py b/configs/ruby/MOESI_CMP_token.py
index 79e0f15f9..20b50e3af 100644
--- a/configs/ruby/MOESI_CMP_token.py
+++ b/configs/ruby/MOESI_CMP_token.py
@@ -125,7 +125,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.port
+            cpu_seq.pio_port = piobus.slave
 
         exec("system.l1_cntrl%d = l1_cntrl" % i)
         #
@@ -201,9 +201,9 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
 
         exec("system.dma_cntrl%d = dma_cntrl" % i)
         if dma_device.type == 'MemTest':
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
         else:
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
         dma_cntrl_nodes.append(dma_cntrl)
 
         cntrl_count += 1
diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index f50315599..3f89a1a90 100644
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -118,7 +118,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.port
+            cpu_seq.pio_port = piobus.slave
 
         if options.recycle_latency:
             l1_cntrl.recycle_latency = options.recycle_latency
@@ -213,9 +213,9 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
 
         exec("system.dma_cntrl%d = dma_cntrl" % i)
         if dma_device.type == 'MemTest':
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
         else:
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
         dma_cntrl_nodes.append(dma_cntrl)
 
         if options.recycle_latency:
diff --git a/configs/ruby/Network_test.py b/configs/ruby/Network_test.py
index bbe7fe844..768b14677 100644
--- a/configs/ruby/Network_test.py
+++ b/configs/ruby/Network_test.py
@@ -96,7 +96,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.port
+            cpu_seq.pio_port = piobus.slave
 
         exec("system.l1_cntrl%d = l1_cntrl" % i)
         #