gpu-compute: AMD's baseline GPU model

6 files changed, 3231 insertions, 0 deletions

diff --git a/configs/ruby/AMD_Base_Constructor.py b/configs/ruby/AMD_Base_Constructor.py
new file mode 100644
index 000000000..d13153e9a
--- /dev/null
+++ b/configs/ruby/AMD_Base_Constructor.py
@@ -0,0 +1,134 @@
+#
+#  Copyright (c) 2015 Advanced Micro Devices, Inc.
+#  All rights reserved.
+#
+#  For use for simulation and test purposes only
+#
+#  Redistribution and use in source and binary forms, with or without
+#  modification, are permitted provided that the following conditions are met:
+#
+#  1. Redistributions of source code must retain the above copyright notice,
+#  this list of conditions and the following disclaimer.
+#
+#  2. Redistributions in binary form must reproduce the above copyright notice,
+#  this list of conditions and the following disclaimer in the documentation
+#  and/or other materials provided with the distribution.
+#
+#  3. Neither the name of the copyright holder nor the names of its contributors
+#  may be used to endorse or promote products derived from this software
+#  without specific prior written permission.
+#
+#  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+#  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+#  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+#  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+#  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+#  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+#  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+#  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+#  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+#  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+#  POSSIBILITY OF SUCH DAMAGE.
+#
+#  Author: Sooraj Puthoor, Lisa Hsu
+#
+
+import math
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+from m5.util import convert
+from CntrlBase import *
+from Cluster import Cluster
+
+#
+# Note: the L1 Cache latency is only used by the sequencer on fast path hits
+#
+class L1Cache(RubyCache):
+    latency = 1
+    resourceStalls = False
+    def create(self, size, assoc, options):
+        self.size = MemorySize(size)
+        self.assoc = assoc
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+#
+# Note: the L2 Cache latency is not currently used
+#
+class L2Cache(RubyCache):
+    latency = 10
+    resourceStalls = False
+    def create(self, size, assoc, options):
+        self.size = MemorySize(size)
+        self.assoc = assoc
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+class CPCntrl(AMD_Base_Controller, CntrlBase):
+
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+        self.cntrl_id = self.cntrlCount()
+
+        self.L1Icache = L1Cache()
+        self.L1Icache.create(options.l1i_size, options.l1i_assoc, options)
+        self.L1D0cache = L1Cache()
+        self.L1D0cache.create(options.l1d_size, options.l1d_assoc, options)
+        self.L1D1cache = L1Cache()
+        self.L1D1cache.create(options.l1d_size, options.l1d_assoc, options)
+        self.L2cache = L2Cache()
+        self.L2cache.create(options.l2_size, options.l2_assoc, options)
+
+        self.sequencer = RubySequencer()
+        self.sequencer.version = self.seqCount()
+        self.sequencer.icache = self.L1Icache
+        self.sequencer.dcache = self.L1D0cache
+        self.sequencer.ruby_system = ruby_system
+        self.sequencer.coreid = 0
+        self.sequencer.is_cpu_sequencer = True
+
+        self.sequencer1 = RubySequencer()
+        self.sequencer1.version = self.seqCount()
+        self.sequencer1.icache = self.L1Icache
+        self.sequencer1.dcache = self.L1D1cache
+        self.sequencer1.ruby_system = ruby_system
+        self.sequencer1.coreid = 1
+        self.sequencer1.is_cpu_sequencer = True
+
+        self.issue_latency = options.cpu_to_dir_latency
+        self.send_evictions = send_evicts(options)
+
+        self.ruby_system = ruby_system
+
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+def define_options(parser):
+    parser.add_option("--cpu-to-dir-latency", type="int", default=15)
+
+def construct(options, system, ruby_system):
+    if (buildEnv['PROTOCOL'] != 'GPU_VIPER' or
+        buildEnv['PROTOCOL'] != 'GPU_VIPER_Region' or
+        buildEnv['PROTOCOL'] != 'GPU_VIPER_Baseline'):
+        panic("This script requires VIPER based protocols \
+        to be built.")
+    cpu_sequencers = []
+    cpuCluster = None
+    cpuCluster = Cluster(name="CPU Cluster", extBW = 8, intBW=8) # 16 GB/s
+    for i in xrange((options.num_cpus + 1) / 2):
+
+        cp_cntrl = CPCntrl()
+        cp_cntrl.create(options, ruby_system, system)
+
+        # Connect the CP controllers to the ruby network
+        cp_cntrl.requestFromCore = ruby_system.network.slave
+        cp_cntrl.responseFromCore = ruby_system.network.slave
+        cp_cntrl.unblockFromCore = ruby_system.network.slave
+        cp_cntrl.probeToCore = ruby_system.network.master
+        cp_cntrl.responseToCore = ruby_system.network.master
+
+        exec("system.cp_cntrl%d = cp_cntrl" % i)
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1])
+        cpuCluster.add(cp_cntrl)
+    return cpu_sequencers, cpuCluster
diff --git a/configs/ruby/GPU_RfO.py b/configs/ruby/GPU_RfO.py
new file mode 100644
index 000000000..bb14252f3
--- /dev/null
+++ b/configs/ruby/GPU_RfO.py
@@ -0,0 +1,751 @@
+#
+#  Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
+#  All rights reserved.
+#
+#  For use for simulation and test purposes only
+#
+#  Redistribution and use in source and binary forms, with or without
+#  modification, are permitted provided that the following conditions are met:
+#
+#  1. Redistributions of source code must retain the above copyright notice,
+#  this list of conditions and the following disclaimer.
+#
+#  2. Redistributions in binary form must reproduce the above copyright notice,
+#  this list of conditions and the following disclaimer in the documentation
+#  and/or other materials provided with the distribution.
+#
+#  3. Neither the name of the copyright holder nor the names of its contributors
+#  may be used to endorse or promote products derived from this software
+#  without specific prior written permission.
+#
+#  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+#  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+#  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+#  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+#  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+#  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+#  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+#  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+#  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+#  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+#  POSSIBILITY OF SUCH DAMAGE.
+#
+#  Author: Lisa Hsu
+#
+
+import math
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+from Ruby import create_topology
+from Ruby import send_evicts
+
+from Cluster import Cluster
+from Crossbar import Crossbar
+
+class CntrlBase:
+    _seqs = 0
+    @classmethod
+    def seqCount(cls):
+        # Use SeqCount not class since we need global count
+        CntrlBase._seqs += 1
+        return CntrlBase._seqs - 1
+
+    _cntrls = 0
+    @classmethod
+    def cntrlCount(cls):
+        # Use CntlCount not class since we need global count
+        CntrlBase._cntrls += 1
+        return CntrlBase._cntrls - 1
+
+    _version = 0
+    @classmethod
+    def versionCount(cls):
+        cls._version += 1 # Use count for this particular type
+        return cls._version - 1
+
+class TccDirCache(RubyCache):
+    size = "512kB"
+    assoc = 16
+    resourceStalls = False
+    def create(self, options):
+        self.size = MemorySize(options.tcc_size)
+        self.size.value += (options.num_compute_units *
+                            (MemorySize(options.tcp_size).value) *
+                            options.tcc_dir_factor) / long(options.num_tccs)
+        self.start_index_bit = math.log(options.cacheline_size, 2) + \
+                               math.log(options.num_tccs, 2)
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+class L1DCache(RubyCache):
+    resourceStalls = False
+    def create(self, options):
+        self.size = MemorySize(options.l1d_size)
+        self.assoc = options.l1d_assoc
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+class L1ICache(RubyCache):
+    resourceStalls = False
+    def create(self, options):
+        self.size = MemorySize(options.l1i_size)
+        self.assoc = options.l1i_assoc
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+class L2Cache(RubyCache):
+    resourceStalls = False
+    def create(self, options):
+        self.size = MemorySize(options.l2_size)
+        self.assoc = options.l2_assoc
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+
+class CPCntrl(CorePair_Controller, CntrlBase):
+
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+
+        self.L1Icache = L1ICache()
+        self.L1Icache.create(options)
+        self.L1D0cache = L1DCache()
+        self.L1D0cache.create(options)
+        self.L1D1cache = L1DCache()
+        self.L1D1cache.create(options)
+        self.L2cache = L2Cache()
+        self.L2cache.create(options)
+
+        self.sequencer = RubySequencer()
+        self.sequencer.icache_hit_latency = 2
+        self.sequencer.dcache_hit_latency = 2
+        self.sequencer.version = self.seqCount()
+        self.sequencer.icache = self.L1Icache
+        self.sequencer.dcache = self.L1D0cache
+        self.sequencer.ruby_system = ruby_system
+        self.sequencer.coreid = 0
+        self.sequencer.is_cpu_sequencer = True
+
+        self.sequencer1 = RubySequencer()
+        self.sequencer1.version = self.seqCount()
+        self.sequencer1.icache = self.L1Icache
+        self.sequencer1.dcache = self.L1D1cache
+        self.sequencer1.icache_hit_latency = 2
+        self.sequencer1.dcache_hit_latency = 2
+        self.sequencer1.ruby_system = ruby_system
+        self.sequencer1.coreid = 1
+        self.sequencer1.is_cpu_sequencer = True
+
+        self.issue_latency = options.cpu_to_dir_latency
+        self.send_evictions = send_evicts(options)
+
+        self.ruby_system = ruby_system
+
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+class TCPCache(RubyCache):
+    assoc = 8
+    dataArrayBanks = 16
+    tagArrayBanks = 4
+    dataAccessLatency = 4
+    tagAccessLatency = 1
+    def create(self, options):
+        self.size = MemorySize(options.tcp_size)
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+class TCPCntrl(TCP_Controller, CntrlBase):
+
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+
+        self.L1cache = TCPCache(tagAccessLatency = options.TCP_latency)
+        self.L1cache.resourceStalls = options.no_resource_stalls
+        self.L1cache.create(options)
+
+        self.coalescer = RubyGPUCoalescer()
+        self.coalescer.version = self.seqCount()
+        self.coalescer.icache = self.L1cache
+        self.coalescer.dcache = self.L1cache
+        self.coalescer.ruby_system = ruby_system
+        self.coalescer.support_inst_reqs = False
+        self.coalescer.is_cpu_sequencer = False
+        self.coalescer.max_outstanding_requests = options.simds_per_cu * \
+                                                  options.wfs_per_simd * \
+                                                  options.wf_size
+
+        self.sequencer = RubySequencer()
+        self.sequencer.version = self.seqCount()
+        self.sequencer.icache = self.L1cache
+        self.sequencer.dcache = self.L1cache
+        self.sequencer.ruby_system = ruby_system
+        self.sequencer.is_cpu_sequencer = True
+
+        self.use_seq_not_coal = False
+
+        self.ruby_system = ruby_system
+
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+    def createCP(self, options, ruby_system, system):
+        self.version = self.versionCount()
+
+        self.L1cache = TCPCache(tagAccessLatency = options.TCP_latency)
+        self.L1cache.resourceStalls = options.no_resource_stalls
+        self.L1cache.create(options)
+
+        self.coalescer = RubyGPUCoalescer()
+        self.coalescer.version = self.seqCount()
+        self.coalescer.icache = self.L1cache
+        self.coalescer.dcache = self.L1cache
+        self.coalescer.ruby_system = ruby_system
+        self.coalescer.support_inst_reqs = False
+        self.coalescer.is_cpu_sequencer = False
+
+        self.sequencer = RubySequencer()
+        self.sequencer.version = self.seqCount()
+        self.sequencer.icache = self.L1cache
+        self.sequencer.dcache = self.L1cache
+        self.sequencer.ruby_system = ruby_system
+        self.sequencer.is_cpu_sequencer = True
+
+        self.use_seq_not_coal = True
+
+        self.ruby_system = ruby_system
+
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+class SQCCache(RubyCache):
+    size = "32kB"
+    assoc = 8
+    dataArrayBanks = 16
+    tagArrayBanks = 4
+    dataAccessLatency = 4
+    tagAccessLatency = 1
+    def create(self, options):
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+class SQCCntrl(SQC_Controller, CntrlBase):
+
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+
+        self.L1cache = SQCCache()
+        self.L1cache.create(options)
+        self.L1cache.resourceStalls = options.no_resource_stalls
+
+        self.sequencer = RubySequencer()
+
+        self.sequencer.version = self.seqCount()
+        self.sequencer.icache = self.L1cache
+        self.sequencer.dcache = self.L1cache
+        self.sequencer.ruby_system = ruby_system
+        self.sequencer.support_data_reqs = False
+        self.sequencer.is_cpu_sequencer = False
+
+        self.ruby_system = ruby_system
+
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+    def createCP(self, options, ruby_system, system):
+        self.version = self.versionCount()
+
+        self.L1cache = SQCCache()
+        self.L1cache.create(options)
+        self.L1cache.resourceStalls = options.no_resource_stalls
+
+        self.sequencer = RubySequencer()
+
+        self.sequencer.version = self.seqCount()
+        self.sequencer.icache = self.L1cache
+        self.sequencer.dcache = self.L1cache
+        self.sequencer.ruby_system = ruby_system
+        self.sequencer.support_data_reqs = False
+
+        self.ruby_system = ruby_system
+
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+
+class TCC(RubyCache):
+    assoc = 16
+    dataAccessLatency = 8
+    tagAccessLatency = 2
+    resourceStalls = True
+    def create(self, options):
+        self.size = MemorySize(options.tcc_size)
+        self.size = self.size / options.num_tccs
+        self.dataArrayBanks = 256 / options.num_tccs #number of data banks
+        self.tagArrayBanks = 256 / options.num_tccs #number of tag banks
+        if ((self.size.value / long(self.assoc)) < 128):
+            self.size.value = long(128 * self.assoc)
+        self.start_index_bit = math.log(options.cacheline_size, 2) + \
+                               math.log(options.num_tccs, 2)
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+class TCCCntrl(TCC_Controller, CntrlBase):
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+        self.L2cache = TCC()
+        self.L2cache.create(options)
+        self.l2_response_latency = options.TCC_latency
+
+        self.number_of_TBEs = 2048
+
+        self.ruby_system = ruby_system
+
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+    def connectWireBuffers(self, req_to_tccdir, resp_to_tccdir,
+                           tcc_unblock_to_tccdir, req_to_tcc,
+                           probe_to_tcc, resp_to_tcc):
+        self.w_reqToTCCDir = req_to_tccdir
+        self.w_respToTCCDir = resp_to_tccdir
+        self.w_TCCUnblockToTCCDir = tcc_unblock_to_tccdir
+        self.w_reqToTCC = req_to_tcc
+        self.w_probeToTCC = probe_to_tcc
+        self.w_respToTCC = resp_to_tcc
+
+class TCCDirCntrl(TCCdir_Controller, CntrlBase):
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+
+        self.directory = TccDirCache()
+        self.directory.create(options)
+
+        self.number_of_TBEs = 1024
+
+        self.ruby_system = ruby_system
+
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+    def connectWireBuffers(self, req_to_tccdir, resp_to_tccdir,
+                           tcc_unblock_to_tccdir, req_to_tcc,
+                           probe_to_tcc, resp_to_tcc):
+        self.w_reqToTCCDir = req_to_tccdir
+        self.w_respToTCCDir = resp_to_tccdir
+        self.w_TCCUnblockToTCCDir = tcc_unblock_to_tccdir
+        self.w_reqToTCC = req_to_tcc
+        self.w_probeToTCC = probe_to_tcc
+        self.w_respToTCC = resp_to_tcc
+
+class L3Cache(RubyCache):
+    assoc = 8
+    dataArrayBanks = 256
+    tagArrayBanks = 256
+
+    def create(self, options, ruby_system, system):
+        self.size = MemorySize(options.l3_size)
+        self.size.value /= options.num_dirs
+        self.dataArrayBanks /= options.num_dirs
+        self.tagArrayBanks /= options.num_dirs
+        self.dataArrayBanks /= options.num_dirs
+        self.tagArrayBanks /= options.num_dirs
+        self.dataAccessLatency = options.l3_data_latency
+        self.tagAccessLatency = options.l3_tag_latency
+        self.resourceStalls = options.no_resource_stalls
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+class L3Cntrl(L3Cache_Controller, CntrlBase):
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+        self.L3cache = L3Cache()
+        self.L3cache.create(options, ruby_system, system)
+
+        self.l3_response_latency = max(self.L3cache.dataAccessLatency,
+                                       self.L3cache.tagAccessLatency)
+        self.ruby_system = ruby_system
+
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+    def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir,
+                           req_to_l3, probe_to_l3, resp_to_l3):
+        self.reqToDir = req_to_dir
+        self.respToDir = resp_to_dir
+        self.l3UnblockToDir = l3_unblock_to_dir
+        self.reqToL3 = req_to_l3
+        self.probeToL3 = probe_to_l3
+        self.respToL3 = resp_to_l3
+
+class DirMem(RubyDirectoryMemory, CntrlBase):
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+
+        phys_mem_size = AddrRange(options.mem_size).size()
+        mem_module_size = phys_mem_size / options.num_dirs
+        dir_size = MemorySize('0B')
+        dir_size.value = mem_module_size
+        self.size = dir_size
+
+class DirCntrl(Directory_Controller, CntrlBase):
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+
+        self.response_latency = 30
+
+        self.directory = DirMem()
+        self.directory.create(options, ruby_system, system)
+
+        self.L3CacheMemory = L3Cache()
+        self.L3CacheMemory.create(options, ruby_system, system)
+
+        self.l3_hit_latency = max(self.L3CacheMemory.dataAccessLatency,
+                                  self.L3CacheMemory.tagAccessLatency)
+
+        self.number_of_TBEs = options.num_tbes
+
+        self.ruby_system = ruby_system
+
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+    def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir,
+                           req_to_l3, probe_to_l3, resp_to_l3):
+        self.reqToDir = req_to_dir
+        self.respToDir = resp_to_dir
+        self.l3UnblockToDir = l3_unblock_to_dir
+        self.reqToL3 = req_to_l3
+        self.probeToL3 = probe_to_l3
+        self.respToL3 = resp_to_l3
+
+
+
+def define_options(parser):
+    parser.add_option("--num-subcaches", type="int", default=4)
+    parser.add_option("--l3-data-latency", type="int", default=20)
+    parser.add_option("--l3-tag-latency", type="int", default=15)
+    parser.add_option("--cpu-to-dir-latency", type="int", default=15)
+    parser.add_option("--gpu-to-dir-latency", type="int", default=160)
+    parser.add_option("--no-resource-stalls", action="store_false",
+                      default=True)
+    parser.add_option("--num-tbes", type="int", default=256)
+    parser.add_option("--l2-latency", type="int", default=50) # load to use
+    parser.add_option("--num-tccs", type="int", default=1,
+                      help="number of TCC directories and banks in the GPU")
+    parser.add_option("--TCP_latency", type="int", default=4,
+                      help="TCP latency")
+    parser.add_option("--TCC_latency", type="int", default=16,
+                      help="TCC latency")
+    parser.add_option("--tcc-size", type='string', default='256kB',
+                      help="agregate tcc size")
+    parser.add_option("--tcp-size", type='string', default='16kB',
+                      help="tcp size")
+    parser.add_option("--tcc-dir-factor", type='int', default=4,
+                      help="TCCdir size = factor *(TCPs + TCC)")
+
+def create_system(options, full_system, system, dma_devices, ruby_system):
+    if buildEnv['PROTOCOL'] != 'GPU_RfO':
+        panic("This script requires the GPU_RfO protocol to be built.")
+
+    cpu_sequencers = []
+
+    #
+    # The ruby network creation expects the list of nodes in the system to be
+    # consistent with the NetDest list.  Therefore the l1 controller nodes
+    # must be listed before the directory nodes and directory nodes before
+    # dma nodes, etc.
+    #
+    cp_cntrl_nodes = []
+    tcp_cntrl_nodes = []
+    sqc_cntrl_nodes = []
+    tcc_cntrl_nodes = []
+    tccdir_cntrl_nodes = []
+    dir_cntrl_nodes = []
+    l3_cntrl_nodes = []
+
+    #
+    # Must create the individual controllers before the network to ensure the
+    # controller constructors are called before the network constructor
+    #
+
+    TCC_bits = int(math.log(options.num_tccs, 2))
+
+    # This is the base crossbar that connects the L3s, Dirs, and cpu/gpu
+    # Clusters
+    mainCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s
+    for i in xrange(options.num_dirs):
+
+        dir_cntrl = DirCntrl(TCC_select_num_bits = TCC_bits)
+        dir_cntrl.create(options, ruby_system, system)
+        dir_cntrl.number_of_TBEs = 2560 * options.num_compute_units
+        #Enough TBEs for all TCP TBEs
+
+        # Connect the Directory controller to the ruby network
+        dir_cntrl.requestFromCores = MessageBuffer(ordered = True)
+        dir_cntrl.requestFromCores.slave = ruby_system.network.master
+
+        dir_cntrl.responseFromCores = MessageBuffer()
+        dir_cntrl.responseFromCores.slave = ruby_system.network.master
+
+        dir_cntrl.unblockFromCores = MessageBuffer()
+        dir_cntrl.unblockFromCores.slave = ruby_system.network.master
+
+        dir_cntrl.probeToCore = MessageBuffer()
+        dir_cntrl.probeToCore.master = ruby_system.network.slave
+
+        dir_cntrl.responseToCore = MessageBuffer()
+        dir_cntrl.responseToCore.master = ruby_system.network.slave
+
+        dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
+        dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True)
+        dir_cntrl.responseFromMemory = MessageBuffer()
+
+        exec("system.dir_cntrl%d = dir_cntrl" % i)
+        dir_cntrl_nodes.append(dir_cntrl)
+
+        mainCluster.add(dir_cntrl)
+
+    # For an odd number of CPUs, still create the right number of controllers
+    cpuCluster = Cluster(extBW = 512, intBW = 512)  # 1 TB/s
+    for i in xrange((options.num_cpus + 1) / 2):
+
+        cp_cntrl = CPCntrl()
+        cp_cntrl.create(options, ruby_system, system)
+
+        exec("system.cp_cntrl%d = cp_cntrl" % i)
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1])
+
+        # Connect the CP controllers and the network
+        cp_cntrl.requestFromCore = MessageBuffer()
+        cp_cntrl.requestFromCore.master = ruby_system.network.slave
+
+        cp_cntrl.responseFromCore = MessageBuffer()
+        cp_cntrl.responseFromCore.master = ruby_system.network.slave
+
+        cp_cntrl.unblockFromCore = MessageBuffer()
+        cp_cntrl.unblockFromCore.master = ruby_system.network.slave
+
+        cp_cntrl.probeToCore = MessageBuffer()
+        cp_cntrl.probeToCore.slave = ruby_system.network.master
+
+        cp_cntrl.responseToCore = MessageBuffer()
+        cp_cntrl.responseToCore.slave = ruby_system.network.master
+
+        cp_cntrl.mandatoryQueue = MessageBuffer()
+        cp_cntrl.triggerQueue = MessageBuffer(ordered = True)
+
+        cpuCluster.add(cp_cntrl)
+
+    gpuCluster = Cluster(extBW = 512, intBW = 512)  # 1 TB/s
+
+    for i in xrange(options.num_compute_units):
+
+        tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits,
+                             number_of_TBEs = 2560) # max outstanding requests
+        tcp_cntrl.create(options, ruby_system, system)
+
+        exec("system.tcp_cntrl%d = tcp_cntrl" % i)
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.append(tcp_cntrl.coalescer)
+        tcp_cntrl_nodes.append(tcp_cntrl)
+
+        # Connect the TCP controller to the ruby network
+        tcp_cntrl.requestFromTCP = MessageBuffer(ordered = True)
+        tcp_cntrl.requestFromTCP.master = ruby_system.network.slave
+
+        tcp_cntrl.responseFromTCP = MessageBuffer(ordered = True)
+        tcp_cntrl.responseFromTCP.master = ruby_system.network.slave
+
+        tcp_cntrl.unblockFromCore = MessageBuffer(ordered = True)
+        tcp_cntrl.unblockFromCore.master = ruby_system.network.slave
+
+        tcp_cntrl.probeToTCP = MessageBuffer(ordered = True)
+        tcp_cntrl.probeToTCP.slave = ruby_system.network.master
+
+        tcp_cntrl.responseToTCP = MessageBuffer(ordered = True)
+        tcp_cntrl.responseToTCP.slave = ruby_system.network.master
+
+        tcp_cntrl.mandatoryQueue = MessageBuffer()
+
+        gpuCluster.add(tcp_cntrl)
+
+    for i in xrange(options.num_sqc):
+
+        sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits)
+        sqc_cntrl.create(options, ruby_system, system)
+
+        exec("system.sqc_cntrl%d = sqc_cntrl" % i)
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.append(sqc_cntrl.sequencer)
+
+        # Connect the SQC controller to the ruby network
+        sqc_cntrl.requestFromSQC = MessageBuffer(ordered = True)
+        sqc_cntrl.requestFromSQC.master = ruby_system.network.slave
+
+        sqc_cntrl.responseFromSQC = MessageBuffer(ordered = True)
+        sqc_cntrl.responseFromSQC.master = ruby_system.network.slave
+
+        sqc_cntrl.unblockFromCore = MessageBuffer(ordered = True)
+        sqc_cntrl.unblockFromCore.master = ruby_system.network.slave
+
+        sqc_cntrl.probeToSQC = MessageBuffer(ordered = True)
+        sqc_cntrl.probeToSQC.slave = ruby_system.network.master
+
+        sqc_cntrl.responseToSQC = MessageBuffer(ordered = True)
+        sqc_cntrl.responseToSQC.slave = ruby_system.network.master
+
+        sqc_cntrl.mandatoryQueue = MessageBuffer()
+
+        # SQC also in GPU cluster
+        gpuCluster.add(sqc_cntrl)
+
+    for i in xrange(options.numCPs):
+
+        tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits,
+                             number_of_TBEs = 2560) # max outstanding requests
+        tcp_cntrl.createCP(options, ruby_system, system)
+
+        exec("system.tcp_cntrl%d = tcp_cntrl" % (options.num_compute_units + i))
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.append(tcp_cntrl.sequencer)
+        tcp_cntrl_nodes.append(tcp_cntrl)
+
+        # Connect the TCP controller to the ruby network
+        tcp_cntrl.requestFromTCP = MessageBuffer(ordered = True)
+        tcp_cntrl.requestFromTCP.master = ruby_system.network.slave
+
+        tcp_cntrl.responseFromTCP = MessageBuffer(ordered = True)
+        tcp_cntrl.responseFromTCP.master = ruby_system.network.slave
+
+        tcp_cntrl.unblockFromCore = MessageBuffer(ordered = True)
+        tcp_cntrl.unblockFromCore.master = ruby_system.network.slave
+
+        tcp_cntrl.probeToTCP = MessageBuffer(ordered = True)
+        tcp_cntrl.probeToTCP.slave = ruby_system.network.master
+
+        tcp_cntrl.responseToTCP = MessageBuffer(ordered = True)
+        tcp_cntrl.responseToTCP.slave = ruby_system.network.master
+
+        tcp_cntrl.mandatoryQueue = MessageBuffer()
+
+        gpuCluster.add(tcp_cntrl)
+
+        sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits)
+        sqc_cntrl.createCP(options, ruby_system, system)
+
+        exec("system.sqc_cntrl%d = sqc_cntrl" % (options.num_compute_units + i))
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.append(sqc_cntrl.sequencer)
+
+        # Connect the SQC controller to the ruby network
+        sqc_cntrl.requestFromSQC = MessageBuffer(ordered = True)
+        sqc_cntrl.requestFromSQC.master = ruby_system.network.slave
+
+        sqc_cntrl.responseFromSQC = MessageBuffer(ordered = True)
+        sqc_cntrl.responseFromSQC.master = ruby_system.network.slave
+
+        sqc_cntrl.unblockFromCore = MessageBuffer(ordered = True)
+        sqc_cntrl.unblockFromCore.master = ruby_system.network.slave
+
+        sqc_cntrl.probeToSQC = MessageBuffer(ordered = True)
+        sqc_cntrl.probeToSQC.slave = ruby_system.network.master
+
+        sqc_cntrl.responseToSQC = MessageBuffer(ordered = True)
+        sqc_cntrl.responseToSQC.slave = ruby_system.network.master
+
+        sqc_cntrl.mandatoryQueue = MessageBuffer()
+
+        # SQC also in GPU cluster
+        gpuCluster.add(sqc_cntrl)
+
+    for i in xrange(options.num_tccs):
+
+        tcc_cntrl = TCCCntrl(TCC_select_num_bits = TCC_bits,
+                             number_of_TBEs = options.num_compute_units * 2560)
+        #Enough TBEs for all TCP TBEs
+        tcc_cntrl.create(options, ruby_system, system)
+        tcc_cntrl_nodes.append(tcc_cntrl)
+
+        tccdir_cntrl = TCCDirCntrl(TCC_select_num_bits = TCC_bits,
+                              number_of_TBEs = options.num_compute_units * 2560)
+        #Enough TBEs for all TCP TBEs
+        tccdir_cntrl.create(options, ruby_system, system)
+        tccdir_cntrl_nodes.append(tccdir_cntrl)
+
+        exec("system.tcc_cntrl%d = tcc_cntrl" % i)
+        exec("system.tccdir_cntrl%d = tccdir_cntrl" % i)
+
+        # connect all of the wire buffers between L3 and dirs up
+        req_to_tccdir = RubyWireBuffer()
+        resp_to_tccdir = RubyWireBuffer()
+        tcc_unblock_to_tccdir = RubyWireBuffer()
+        req_to_tcc = RubyWireBuffer()
+        probe_to_tcc = RubyWireBuffer()
+        resp_to_tcc = RubyWireBuffer()
+
+        tcc_cntrl.connectWireBuffers(req_to_tccdir, resp_to_tccdir,
+                                     tcc_unblock_to_tccdir, req_to_tcc,
+                                     probe_to_tcc, resp_to_tcc)
+        tccdir_cntrl.connectWireBuffers(req_to_tccdir, resp_to_tccdir,
+                                        tcc_unblock_to_tccdir, req_to_tcc,
+                                        probe_to_tcc, resp_to_tcc)
+
+        # Connect the TCC controller to the ruby network
+        tcc_cntrl.responseFromTCC = MessageBuffer(ordered = True)
+        tcc_cntrl.responseFromTCC.master = ruby_system.network.slave
+
+        tcc_cntrl.responseToTCC = MessageBuffer(ordered = True)
+        tcc_cntrl.responseToTCC.slave = ruby_system.network.master
+
+        # Connect the TCC Dir controller to the ruby network
+        tccdir_cntrl.requestFromTCP = MessageBuffer(ordered = True)
+        tccdir_cntrl.requestFromTCP.slave = ruby_system.network.master
+
+        tccdir_cntrl.responseFromTCP = MessageBuffer(ordered = True)
+        tccdir_cntrl.responseFromTCP.slave = ruby_system.network.master
+
+        tccdir_cntrl.unblockFromTCP = MessageBuffer(ordered = True)
+        tccdir_cntrl.unblockFromTCP.slave = ruby_system.network.master
+
+        tccdir_cntrl.probeToCore = MessageBuffer(ordered = True)
+        tccdir_cntrl.probeToCore.master = ruby_system.network.slave
+
+        tccdir_cntrl.responseToCore = MessageBuffer(ordered = True)
+        tccdir_cntrl.responseToCore.master = ruby_system.network.slave
+
+        tccdir_cntrl.probeFromNB = MessageBuffer()
+        tccdir_cntrl.probeFromNB.slave = ruby_system.network.master
+
+        tccdir_cntrl.responseFromNB = MessageBuffer()
+        tccdir_cntrl.responseFromNB.slave = ruby_system.network.master
+
+        tccdir_cntrl.requestToNB = MessageBuffer()
+        tccdir_cntrl.requestToNB.master = ruby_system.network.slave
+
+        tccdir_cntrl.responseToNB = MessageBuffer()
+        tccdir_cntrl.responseToNB.master = ruby_system.network.slave
+
+        tccdir_cntrl.unblockToNB = MessageBuffer()
+        tccdir_cntrl.unblockToNB.master = ruby_system.network.slave
+
+        tccdir_cntrl.triggerQueue = MessageBuffer(ordered = True)
+
+        # TCC cntrls added to the GPU cluster
+        gpuCluster.add(tcc_cntrl)
+        gpuCluster.add(tccdir_cntrl)
+
+    # Assuming no DMA devices
+    assert(len(dma_devices) == 0)
+
+    # Add cpu/gpu clusters to main cluster
+    mainCluster.add(cpuCluster)
+    mainCluster.add(gpuCluster)
+
+    ruby_system.network.number_of_virtual_networks = 10
+
+    return (cpu_sequencers, dir_cntrl_nodes, mainCluster)
diff --git a/configs/ruby/GPU_VIPER.py b/configs/ruby/GPU_VIPER.py
new file mode 100644
index 000000000..f1384c404
--- /dev/null
+++ b/configs/ruby/GPU_VIPER.py
@@ -0,0 +1,674 @@
+#
+#  Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
+#  All rights reserved.
+#
+#  For use for simulation and test purposes only
+#
+#  Redistribution and use in source and binary forms, with or without
+#  modification, are permitted provided that the following conditions are met:
+#
+#  1. Redistributions of source code must retain the above copyright notice,
+#  this list of conditions and the following disclaimer.
+#
+#  2. Redistributions in binary form must reproduce the above copyright notice,
+#  this list of conditions and the following disclaimer in the documentation
+#  and/or other materials provided with the distribution.
+#
+#  3. Neither the name of the copyright holder nor the names of its contributors
+#  may be used to endorse or promote products derived from this software
+#  without specific prior written permission.
+#
+#  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+#  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+#  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+#  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+#  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+#  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+#  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+#  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+#  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+#  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+#  POSSIBILITY OF SUCH DAMAGE.
+#
+#  Author: Lisa Hsu
+#
+
+import math
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+from Ruby import create_topology
+from Ruby import send_evicts
+
+from Cluster import Cluster
+from Crossbar import Crossbar
+
+class CntrlBase:
+    _seqs = 0
+    @classmethod
+    def seqCount(cls):
+        # Use SeqCount not class since we need global count
+        CntrlBase._seqs += 1
+        return CntrlBase._seqs - 1
+
+    _cntrls = 0
+    @classmethod
+    def cntrlCount(cls):
+        # Use CntlCount not class since we need global count
+        CntrlBase._cntrls += 1
+        return CntrlBase._cntrls - 1
+
+    _version = 0
+    @classmethod
+    def versionCount(cls):
+        cls._version += 1 # Use count for this particular type
+        return cls._version - 1
+
+class L1Cache(RubyCache):
+    resourceStalls = False
+    dataArrayBanks = 2
+    tagArrayBanks = 2
+    dataAccessLatency = 1
+    tagAccessLatency = 1
+    def create(self, size, assoc, options):
+        self.size = MemorySize(size)
+        self.assoc = assoc
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+class L2Cache(RubyCache):
+    resourceStalls = False
+    assoc = 16
+    dataArrayBanks = 16
+    tagArrayBanks = 16
+    def create(self, size, assoc, options):
+        self.size = MemorySize(size)
+        self.assoc = assoc
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+class CPCntrl(CorePair_Controller, CntrlBase):
+
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+
+        self.L1Icache = L1Cache()
+        self.L1Icache.create(options.l1i_size, options.l1i_assoc, options)
+        self.L1D0cache = L1Cache()
+        self.L1D0cache.create(options.l1d_size, options.l1d_assoc, options)
+        self.L1D1cache = L1Cache()
+        self.L1D1cache.create(options.l1d_size, options.l1d_assoc, options)
+        self.L2cache = L2Cache()
+        self.L2cache.create(options.l2_size, options.l2_assoc, options)
+
+        self.sequencer = RubySequencer()
+        self.sequencer.version = self.seqCount()
+        self.sequencer.icache = self.L1Icache
+        self.sequencer.dcache = self.L1D0cache
+        self.sequencer.ruby_system = ruby_system
+        self.sequencer.coreid = 0
+        self.sequencer.is_cpu_sequencer = True
+
+        self.sequencer1 = RubySequencer()
+        self.sequencer1.version = self.seqCount()
+        self.sequencer1.icache = self.L1Icache
+        self.sequencer1.dcache = self.L1D1cache
+        self.sequencer1.ruby_system = ruby_system
+        self.sequencer1.coreid = 1
+        self.sequencer1.is_cpu_sequencer = True
+
+        self.issue_latency = options.cpu_to_dir_latency
+        self.send_evictions = send_evicts(options)
+
+        self.ruby_system = ruby_system
+
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+class TCPCache(RubyCache):
+    size = "16kB"
+    assoc = 16
+    dataArrayBanks = 16 #number of data banks
+    tagArrayBanks = 16  #number of tag banks
+    dataAccessLatency = 4
+    tagAccessLatency = 1
+    def create(self, options):
+        self.size = MemorySize(options.tcp_size)
+        self.assoc = options.tcp_assoc
+        self.resourceStalls = options.no_tcc_resource_stalls
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+class TCPCntrl(TCP_Controller, CntrlBase):
+
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+
+        self.L1cache = TCPCache(tagAccessLatency = options.TCP_latency,
+                                dataAccessLatency = options.TCP_latency)
+        self.L1cache.resourceStalls = options.no_resource_stalls
+        self.L1cache.create(options)
+        self.issue_latency = 1
+
+        self.coalescer = VIPERCoalescer()
+        self.coalescer.version = self.seqCount()
+        self.coalescer.icache = self.L1cache
+        self.coalescer.dcache = self.L1cache
+        self.coalescer.ruby_system = ruby_system
+        self.coalescer.support_inst_reqs = False
+        self.coalescer.is_cpu_sequencer = False
+
+        self.sequencer = RubySequencer()
+        self.sequencer.version = self.seqCount()
+        self.sequencer.icache = self.L1cache
+        self.sequencer.dcache = self.L1cache
+        self.sequencer.ruby_system = ruby_system
+        self.sequencer.is_cpu_sequencer = True
+
+        self.use_seq_not_coal = False
+
+        self.ruby_system = ruby_system
+
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+    def createCP(self, options, ruby_system, system):
+        self.version = self.versionCount()
+
+        self.L1cache = TCPCache(tagAccessLatency = options.TCP_latency,
+                                dataAccessLatency = options.TCP_latency)
+        self.L1cache.resourceStalls = options.no_resource_stalls
+        self.L1cache.create(options)
+        self.issue_latency = 1
+
+        self.coalescer = VIPERCoalescer()
+        self.coalescer.version = self.seqCount()
+        self.coalescer.icache = self.L1cache
+        self.coalescer.dcache = self.L1cache
+        self.coalescer.ruby_system = ruby_system
+        self.coalescer.support_inst_reqs = False
+        self.coalescer.is_cpu_sequencer = False
+
+        self.sequencer = RubySequencer()
+        self.sequencer.version = self.seqCount()
+        self.sequencer.icache = self.L1cache
+        self.sequencer.dcache = self.L1cache
+        self.sequencer.ruby_system = ruby_system
+        self.sequencer.is_cpu_sequencer = True
+
+        self.use_seq_not_coal = True
+
+        self.ruby_system = ruby_system
+
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+class SQCCache(RubyCache):
+    dataArrayBanks = 8
+    tagArrayBanks = 8
+    dataAccessLatency = 1
+    tagAccessLatency = 1
+
+    def create(self, options):
+        self.size = MemorySize(options.sqc_size)
+        self.assoc = options.sqc_assoc
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+class SQCCntrl(SQC_Controller, CntrlBase):
+
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+
+        self.L1cache = SQCCache()
+        self.L1cache.create(options)
+        self.L1cache.resourceStalls = options.no_resource_stalls
+
+        self.sequencer = RubySequencer()
+
+        self.sequencer.version = self.seqCount()
+        self.sequencer.icache = self.L1cache
+        self.sequencer.dcache = self.L1cache
+        self.sequencer.ruby_system = ruby_system
+        self.sequencer.support_data_reqs = False
+        self.sequencer.is_cpu_sequencer = False
+
+        self.ruby_system = ruby_system
+
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+class TCC(RubyCache):
+    size = MemorySize("256kB")
+    assoc = 16
+    dataAccessLatency = 8
+    tagAccessLatency = 2
+    resourceStalls = True
+    def create(self, options):
+        self.assoc = options.tcc_assoc
+        if hasattr(options, 'bw_scalor') and options.bw_scalor > 0:
+          s = options.num_compute_units
+          tcc_size = s * 128
+          tcc_size = str(tcc_size)+'kB'
+          self.size = MemorySize(tcc_size)
+          self.dataArrayBanks = 64
+          self.tagArrayBanks = 64
+        else:
+          self.size = MemorySize(options.tcc_size)
+          self.dataArrayBanks = 256 / options.num_tccs #number of data banks
+          self.tagArrayBanks = 256 / options.num_tccs #number of tag banks
+        self.size.value = self.size.value / options.num_tccs
+        if ((self.size.value / long(self.assoc)) < 128):
+            self.size.value = long(128 * self.assoc)
+        self.start_index_bit = math.log(options.cacheline_size, 2) + \
+                               math.log(options.num_tccs, 2)
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+
+class TCCCntrl(TCC_Controller, CntrlBase):
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+        self.L2cache = TCC()
+        self.L2cache.create(options)
+        self.L2cache.resourceStalls = options.no_tcc_resource_stalls
+
+        self.ruby_system = ruby_system
+
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+class L3Cache(RubyCache):
+    dataArrayBanks = 16
+    tagArrayBanks = 16
+
+    def create(self, options, ruby_system, system):
+        self.size = MemorySize(options.l3_size)
+        self.size.value /= options.num_dirs
+        self.assoc = options.l3_assoc
+        self.dataArrayBanks /= options.num_dirs
+        self.tagArrayBanks /= options.num_dirs
+        self.dataArrayBanks /= options.num_dirs
+        self.tagArrayBanks /= options.num_dirs
+        self.dataAccessLatency = options.l3_data_latency
+        self.tagAccessLatency = options.l3_tag_latency
+        self.resourceStalls = False
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+class L3Cntrl(L3Cache_Controller, CntrlBase):
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+        self.L3cache = L3Cache()
+        self.L3cache.create(options, ruby_system, system)
+
+        self.l3_response_latency = max(self.L3cache.dataAccessLatency, self.L3cache.tagAccessLatency)
+        self.ruby_system = ruby_system
+
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+    def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir,
+                           req_to_l3, probe_to_l3, resp_to_l3):
+        self.reqToDir = req_to_dir
+        self.respToDir = resp_to_dir
+        self.l3UnblockToDir = l3_unblock_to_dir
+        self.reqToL3 = req_to_l3
+        self.probeToL3 = probe_to_l3
+        self.respToL3 = resp_to_l3
+
+class DirMem(RubyDirectoryMemory, CntrlBase):
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+
+        phys_mem_size = AddrRange(options.mem_size).size()
+        mem_module_size = phys_mem_size / options.num_dirs
+        dir_size = MemorySize('0B')
+        dir_size.value = mem_module_size
+        self.size = dir_size
+
+class DirCntrl(Directory_Controller, CntrlBase):
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+
+        self.response_latency = 30
+
+        self.directory = DirMem()
+        self.directory.create(options, ruby_system, system)
+
+        self.L3CacheMemory = L3Cache()
+        self.L3CacheMemory.create(options, ruby_system, system)
+
+        self.l3_hit_latency = max(self.L3CacheMemory.dataAccessLatency,
+                                  self.L3CacheMemory.tagAccessLatency)
+
+        self.number_of_TBEs = options.num_tbes
+
+        self.ruby_system = ruby_system
+
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+    def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir,
+                           req_to_l3, probe_to_l3, resp_to_l3):
+        self.reqToDir = req_to_dir
+        self.respToDir = resp_to_dir
+        self.l3UnblockToDir = l3_unblock_to_dir
+        self.reqToL3 = req_to_l3
+        self.probeToL3 = probe_to_l3
+        self.respToL3 = resp_to_l3
+
+def define_options(parser):
+    parser.add_option("--num-subcaches", type = "int", default = 4)
+    parser.add_option("--l3-data-latency", type = "int", default = 20)
+    parser.add_option("--l3-tag-latency", type = "int", default = 15)
+    parser.add_option("--cpu-to-dir-latency", type = "int", default = 120)
+    parser.add_option("--gpu-to-dir-latency", type = "int", default = 120)
+    parser.add_option("--no-resource-stalls", action = "store_false",
+                      default = True)
+    parser.add_option("--no-tcc-resource-stalls", action = "store_false",
+                      default = True)
+    parser.add_option("--use-L3-on-WT", action = "store_true", default = False)
+    parser.add_option("--num-tbes", type = "int", default = 256)
+    parser.add_option("--l2-latency", type = "int", default = 50)  # load to use
+    parser.add_option("--num-tccs", type = "int", default = 1,
+                      help = "number of TCC banks in the GPU")
+    parser.add_option("--sqc-size", type = 'string', default = '32kB',
+                      help = "SQC cache size")
+    parser.add_option("--sqc-assoc", type = 'int', default = 8,
+                      help = "SQC cache assoc")
+    parser.add_option("--WB_L1", action = "store_true", default = False,
+                      help = "writeback L1")
+    parser.add_option("--WB_L2", action = "store_true", default = False,
+                      help = "writeback L2")
+    parser.add_option("--TCP_latency", type = "int", default = 4,
+                      help = "TCP latency")
+    parser.add_option("--TCC_latency", type = "int", default = 16,
+                      help = "TCC latency")
+    parser.add_option("--tcc-size", type = 'string', default = '256kB',
+                      help = "agregate tcc size")
+    parser.add_option("--tcc-assoc", type = 'int', default = 16,
+                      help = "tcc assoc")
+    parser.add_option("--tcp-size", type = 'string', default = '16kB',
+                      help = "tcp size")
+    parser.add_option("--tcp-assoc", type = 'int', default = 16,
+                      help = "tcp assoc")
+    parser.add_option("--noL1", action = "store_true", default = False,
+                      help = "bypassL1")
+
+def create_system(options, full_system, system, dma_devices, ruby_system):
+    if buildEnv['PROTOCOL'] != 'GPU_VIPER':
+        panic("This script requires the GPU_VIPER protocol to be built.")
+
+    cpu_sequencers = []
+
+    #
+    # The ruby network creation expects the list of nodes in the system to be
+    # consistent with the NetDest list.  Therefore the l1 controller nodes
+    # must be listed before the directory nodes and directory nodes before
+    # dma nodes, etc.
+    #
+    cp_cntrl_nodes = []
+    tcp_cntrl_nodes = []
+    sqc_cntrl_nodes = []
+    tcc_cntrl_nodes = []
+    dir_cntrl_nodes = []
+    l3_cntrl_nodes = []
+
+    #
+    # Must create the individual controllers before the network to ensure the
+    # controller constructors are called before the network constructor
+    #
+
+    # For an odd number of CPUs, still create the right number of controllers
+    TCC_bits = int(math.log(options.num_tccs, 2))
+
+    # This is the base crossbar that connects the L3s, Dirs, and cpu/gpu
+    # Clusters
+    crossbar_bw = None
+    mainCluster = None
+    if hasattr(options, 'bw_scalor') and options.bw_scalor > 0:
+        #Assuming a 2GHz clock
+        crossbar_bw = 16 * options.num_compute_units * options.bw_scalor
+        mainCluster = Cluster(intBW=crossbar_bw)
+    else:
+        mainCluster = Cluster(intBW=8) # 16 GB/s
+    for i in xrange(options.num_dirs):
+
+        dir_cntrl = DirCntrl(noTCCdir = True, TCC_select_num_bits = TCC_bits)
+        dir_cntrl.create(options, ruby_system, system)
+        dir_cntrl.number_of_TBEs = options.num_tbes
+        dir_cntrl.useL3OnWT = options.use_L3_on_WT
+        # the number_of_TBEs is inclusive of TBEs below
+
+        # Connect the Directory controller to the ruby network
+        dir_cntrl.requestFromCores = MessageBuffer(ordered = True)
+        dir_cntrl.requestFromCores.slave = ruby_system.network.master
+
+        dir_cntrl.responseFromCores = MessageBuffer()
+        dir_cntrl.responseFromCores.slave = ruby_system.network.master
+
+        dir_cntrl.unblockFromCores = MessageBuffer()
+        dir_cntrl.unblockFromCores.slave = ruby_system.network.master
+
+        dir_cntrl.probeToCore = MessageBuffer()
+        dir_cntrl.probeToCore.master = ruby_system.network.slave
+
+        dir_cntrl.responseToCore = MessageBuffer()
+        dir_cntrl.responseToCore.master = ruby_system.network.slave
+
+        dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
+        dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True)
+        dir_cntrl.responseFromMemory = MessageBuffer()
+
+        exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
+        dir_cntrl_nodes.append(dir_cntrl)
+
+        mainCluster.add(dir_cntrl)
+
+    cpuCluster = None
+    if hasattr(options, 'bw_scalor') and options.bw_scalor > 0:
+        cpuCluster = Cluster(extBW = crossbar_bw, intBW = crossbar_bw)
+    else:
+        cpuCluster = Cluster(extBW = 8, intBW = 8) # 16 GB/s
+    for i in xrange((options.num_cpus + 1) / 2):
+
+        cp_cntrl = CPCntrl()
+        cp_cntrl.create(options, ruby_system, system)
+
+        exec("ruby_system.cp_cntrl%d = cp_cntrl" % i)
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1])
+
+        # Connect the CP controllers and the network
+        cp_cntrl.requestFromCore = MessageBuffer()
+        cp_cntrl.requestFromCore.master = ruby_system.network.slave
+
+        cp_cntrl.responseFromCore = MessageBuffer()
+        cp_cntrl.responseFromCore.master = ruby_system.network.slave
+
+        cp_cntrl.unblockFromCore = MessageBuffer()
+        cp_cntrl.unblockFromCore.master = ruby_system.network.slave
+
+        cp_cntrl.probeToCore = MessageBuffer()
+        cp_cntrl.probeToCore.slave = ruby_system.network.master
+
+        cp_cntrl.responseToCore = MessageBuffer()
+        cp_cntrl.responseToCore.slave = ruby_system.network.master
+
+        cp_cntrl.mandatoryQueue = MessageBuffer()
+        cp_cntrl.triggerQueue = MessageBuffer(ordered = True)
+
+        cpuCluster.add(cp_cntrl)
+
+    gpuCluster = None
+    if hasattr(options, 'bw_scalor') and options.bw_scalor > 0:
+      gpuCluster = Cluster(extBW = crossbar_bw, intBW = crossbar_bw)
+    else:
+      gpuCluster = Cluster(extBW = 8, intBW = 8) # 16 GB/s
+    for i in xrange(options.num_compute_units):
+
+        tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits,
+                             issue_latency = 1,
+                             number_of_TBEs = 2560)
+        # TBEs set to max outstanding requests
+        tcp_cntrl.create(options, ruby_system, system)
+        tcp_cntrl.WB = options.WB_L1
+        tcp_cntrl.disableL1 = options.noL1
+        tcp_cntrl.L1cache.tagAccessLatency = options.TCP_latency
+        tcp_cntrl.L1cache.dataAccessLatency = options.TCP_latency
+
+        exec("ruby_system.tcp_cntrl%d = tcp_cntrl" % i)
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.append(tcp_cntrl.coalescer)
+        tcp_cntrl_nodes.append(tcp_cntrl)
+
+        # Connect the TCP controller to the ruby network
+        tcp_cntrl.requestFromTCP = MessageBuffer(ordered = True)
+        tcp_cntrl.requestFromTCP.master = ruby_system.network.slave
+
+        tcp_cntrl.responseFromTCP = MessageBuffer(ordered = True)
+        tcp_cntrl.responseFromTCP.master = ruby_system.network.slave
+
+        tcp_cntrl.unblockFromCore = MessageBuffer()
+        tcp_cntrl.unblockFromCore.master = ruby_system.network.slave
+
+        tcp_cntrl.probeToTCP = MessageBuffer(ordered = True)
+        tcp_cntrl.probeToTCP.slave = ruby_system.network.master
+
+        tcp_cntrl.responseToTCP = MessageBuffer(ordered = True)
+        tcp_cntrl.responseToTCP.slave = ruby_system.network.master
+
+        tcp_cntrl.mandatoryQueue = MessageBuffer()
+
+        gpuCluster.add(tcp_cntrl)
+
+    for i in xrange(options.num_sqc):
+
+        sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits)
+        sqc_cntrl.create(options, ruby_system, system)
+
+        exec("ruby_system.sqc_cntrl%d = sqc_cntrl" % i)
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.append(sqc_cntrl.sequencer)
+
+        # Connect the SQC controller to the ruby network
+        sqc_cntrl.requestFromSQC = MessageBuffer(ordered = True)
+        sqc_cntrl.requestFromSQC.master = ruby_system.network.slave
+
+        sqc_cntrl.probeToSQC = MessageBuffer(ordered = True)
+        sqc_cntrl.probeToSQC.slave = ruby_system.network.master
+
+        sqc_cntrl.responseToSQC = MessageBuffer(ordered = True)
+        sqc_cntrl.responseToSQC.slave = ruby_system.network.master
+
+        sqc_cntrl.mandatoryQueue = MessageBuffer()
+
+        # SQC also in GPU cluster
+        gpuCluster.add(sqc_cntrl)
+
+    for i in xrange(options.numCPs):
+
+        tcp_ID = options.num_compute_units + i
+        sqc_ID = options.num_sqc + i
+
+        tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits,
+                             issue_latency = 1,
+                             number_of_TBEs = 2560)
+        # TBEs set to max outstanding requests
+        tcp_cntrl.createCP(options, ruby_system, system)
+        tcp_cntrl.WB = options.WB_L1
+        tcp_cntrl.disableL1 = options.noL1
+        tcp_cntrl.L1cache.tagAccessLatency = options.TCP_latency
+        tcp_cntrl.L1cache.dataAccessLatency = options.TCP_latency
+
+        exec("ruby_system.tcp_cntrl%d = tcp_cntrl" % tcp_ID)
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.append(tcp_cntrl.sequencer)
+        tcp_cntrl_nodes.append(tcp_cntrl)
+
+        # Connect the CP (TCP) controllers to the ruby network
+        tcp_cntrl.requestFromTCP = MessageBuffer(ordered = True)
+        tcp_cntrl.requestFromTCP.master = ruby_system.network.slave
+
+        tcp_cntrl.responseFromTCP = MessageBuffer(ordered = True)
+        tcp_cntrl.responseFromTCP.master = ruby_system.network.slave
+
+        tcp_cntrl.unblockFromCore = MessageBuffer(ordered = True)
+        tcp_cntrl.unblockFromCore.master = ruby_system.network.slave
+
+        tcp_cntrl.probeToTCP = MessageBuffer(ordered = True)
+        tcp_cntrl.probeToTCP.slave = ruby_system.network.master
+
+        tcp_cntrl.responseToTCP = MessageBuffer(ordered = True)
+        tcp_cntrl.responseToTCP.slave = ruby_system.network.master
+
+        tcp_cntrl.mandatoryQueue = MessageBuffer()
+
+        gpuCluster.add(tcp_cntrl)
+
+        sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits)
+        sqc_cntrl.create(options, ruby_system, system)
+
+        exec("ruby_system.sqc_cntrl%d = sqc_cntrl" % sqc_ID)
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.append(sqc_cntrl.sequencer)
+
+        # SQC also in GPU cluster
+        gpuCluster.add(sqc_cntrl)
+
+    for i in xrange(options.num_tccs):
+
+        tcc_cntrl = TCCCntrl(l2_response_latency = options.TCC_latency)
+        tcc_cntrl.create(options, ruby_system, system)
+        tcc_cntrl.l2_request_latency = options.gpu_to_dir_latency
+        tcc_cntrl.l2_response_latency = options.TCC_latency
+        tcc_cntrl_nodes.append(tcc_cntrl)
+        tcc_cntrl.WB = options.WB_L2
+        tcc_cntrl.number_of_TBEs = 2560 * options.num_compute_units
+        # the number_of_TBEs is inclusive of TBEs below
+
+        # Connect the TCC controllers to the ruby network
+        tcc_cntrl.requestFromTCP = MessageBuffer(ordered = True)
+        tcc_cntrl.requestFromTCP.slave = ruby_system.network.master
+
+        tcc_cntrl.responseToCore = MessageBuffer(ordered = True)
+        tcc_cntrl.responseToCore.master = ruby_system.network.slave
+
+        tcc_cntrl.probeFromNB = MessageBuffer()
+        tcc_cntrl.probeFromNB.slave = ruby_system.network.master
+
+        tcc_cntrl.responseFromNB = MessageBuffer()
+        tcc_cntrl.responseFromNB.slave = ruby_system.network.master
+
+        tcc_cntrl.requestToNB = MessageBuffer(ordered = True)
+        tcc_cntrl.requestToNB.master = ruby_system.network.slave
+
+        tcc_cntrl.responseToNB = MessageBuffer()
+        tcc_cntrl.responseToNB.master = ruby_system.network.slave
+
+        tcc_cntrl.unblockToNB = MessageBuffer()
+        tcc_cntrl.unblockToNB.master = ruby_system.network.slave
+
+        tcc_cntrl.triggerQueue = MessageBuffer(ordered = True)
+
+        exec("ruby_system.tcc_cntrl%d = tcc_cntrl" % i)
+
+        # connect all of the wire buffers between L3 and dirs up
+        # TCC cntrls added to the GPU cluster
+        gpuCluster.add(tcc_cntrl)
+
+    # Assuming no DMA devices
+    assert(len(dma_devices) == 0)
+
+    # Add cpu/gpu clusters to main cluster
+    mainCluster.add(cpuCluster)
+    mainCluster.add(gpuCluster)
+
+    ruby_system.network.number_of_virtual_networks = 10
+
+    return (cpu_sequencers, dir_cntrl_nodes, mainCluster)
diff --git a/configs/ruby/GPU_VIPER_Baseline.py b/configs/ruby/GPU_VIPER_Baseline.py
new file mode 100644
index 000000000..879b34e88
--- /dev/null
+++ b/configs/ruby/GPU_VIPER_Baseline.py
@@ -0,0 +1,588 @@
+#
+#  Copyright (c) 2015 Advanced Micro Devices, Inc.
+#  All rights reserved.
+#
+#  For use for simulation and test purposes only
+#
+#  Redistribution and use in source and binary forms, with or without
+#  modification, are permitted provided that the following conditions are met:
+#
+#  1. Redistributions of source code must retain the above copyright notice,
+#  this list of conditions and the following disclaimer.
+#
+#  2. Redistributions in binary form must reproduce the above copyright notice,
+#  this list of conditions and the following disclaimer in the documentation
+#  and/or other materials provided with the distribution.
+#
+#  3. Neither the name of the copyright holder nor the names of its contributors
+#  may be used to endorse or promote products derived from this software
+#  without specific prior written permission.
+#
+#  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+#  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+#  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+#  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+#  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+#  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+#  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+#  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+#  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+#  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+#  POSSIBILITY OF SUCH DAMAGE.
+#
+#  Author: Sooraj Puthoor
+#
+
+import math
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+from Ruby import create_topology
+from Ruby import send_evicts
+
+from Cluster import Cluster
+from Crossbar import Crossbar
+
+class CntrlBase:
+    _seqs = 0
+    @classmethod
+    def seqCount(cls):
+        # Use SeqCount not class since we need global count
+        CntrlBase._seqs += 1
+        return CntrlBase._seqs - 1
+
+    _cntrls = 0
+    @classmethod
+    def cntrlCount(cls):
+        # Use CntlCount not class since we need global count
+        CntrlBase._cntrls += 1
+        return CntrlBase._cntrls - 1
+
+    _version = 0
+    @classmethod
+    def versionCount(cls):
+        cls._version += 1 # Use count for this particular type
+        return cls._version - 1
+
+class L1Cache(RubyCache):
+    resourceStalls = False
+    dataArrayBanks = 2
+    tagArrayBanks = 2
+    dataAccessLatency = 1
+    tagAccessLatency = 1
+    def create(self, size, assoc, options):
+        self.size = MemorySize(size)
+        self.assoc = assoc
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+class L2Cache(RubyCache):
+    resourceStalls = False
+    assoc = 16
+    dataArrayBanks = 16
+    tagArrayBanks = 16
+    def create(self, size, assoc, options):
+        self.size = MemorySize(size)
+        self.assoc = assoc
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+class CPCntrl(CorePair_Controller, CntrlBase):
+
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+
+        self.L1Icache = L1Cache()
+        self.L1Icache.create(options.l1i_size, options.l1i_assoc, options)
+        self.L1D0cache = L1Cache()
+        self.L1D0cache.create(options.l1d_size, options.l1d_assoc, options)
+        self.L1D1cache = L1Cache()
+        self.L1D1cache.create(options.l1d_size, options.l1d_assoc, options)
+        self.L2cache = L2Cache()
+        self.L2cache.create(options.l2_size, options.l2_assoc, options)
+
+        self.sequencer = RubySequencer()
+        self.sequencer.version = self.seqCount()
+        self.sequencer.icache = self.L1Icache
+        self.sequencer.dcache = self.L1D0cache
+        self.sequencer.ruby_system = ruby_system
+        self.sequencer.coreid = 0
+        self.sequencer.is_cpu_sequencer = True
+
+        self.sequencer1 = RubySequencer()
+        self.sequencer1.version = self.seqCount()
+        self.sequencer1.icache = self.L1Icache
+        self.sequencer1.dcache = self.L1D1cache
+        self.sequencer1.ruby_system = ruby_system
+        self.sequencer1.coreid = 1
+        self.sequencer1.is_cpu_sequencer = True
+
+        self.issue_latency = options.cpu_to_dir_latency
+        self.send_evictions = send_evicts(options)
+
+        self.ruby_system = ruby_system
+
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+class TCPCache(RubyCache):
+    size = "16kB"
+    assoc = 16
+    dataArrayBanks = 16
+    tagArrayBanks = 16
+    dataAccessLatency = 4
+    tagAccessLatency = 1
+    def create(self, options):
+        self.size = MemorySize(options.tcp_size)
+        self.dataArrayBanks = 16
+        self.tagArrayBanks = 16
+        self.dataAccessLatency = 4
+        self.tagAccessLatency = 1
+        self.resourceStalls = options.no_tcc_resource_stalls
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+class TCPCntrl(TCP_Controller, CntrlBase):
+
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+        self.L1cache = TCPCache()
+        self.L1cache.create(options)
+        self.issue_latency = 1
+
+        self.coalescer = VIPERCoalescer()
+        self.coalescer.version = self.seqCount()
+        self.coalescer.icache = self.L1cache
+        self.coalescer.dcache = self.L1cache
+        self.coalescer.ruby_system = ruby_system
+        self.coalescer.support_inst_reqs = False
+        self.coalescer.is_cpu_sequencer = False
+
+        self.sequencer = RubySequencer()
+        self.sequencer.version = self.seqCount()
+        self.sequencer.icache = self.L1cache
+        self.sequencer.dcache = self.L1cache
+        self.sequencer.ruby_system = ruby_system
+        self.sequencer.is_cpu_sequencer = True
+
+        self.use_seq_not_coal = False
+
+        self.ruby_system = ruby_system
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+class SQCCache(RubyCache):
+    dataArrayBanks = 8
+    tagArrayBanks = 8
+    dataAccessLatency = 1
+    tagAccessLatency = 1
+
+    def create(self, options):
+        self.size = MemorySize(options.sqc_size)
+        self.assoc = options.sqc_assoc
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+class SQCCntrl(SQC_Controller, CntrlBase):
+
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+        self.L1cache = SQCCache()
+        self.L1cache.create(options)
+        self.L1cache.resourceStalls = False
+        self.sequencer = RubySequencer()
+        self.sequencer.version = self.seqCount()
+        self.sequencer.icache = self.L1cache
+        self.sequencer.dcache = self.L1cache
+        self.sequencer.ruby_system = ruby_system
+        self.sequencer.support_data_reqs = False
+        self.sequencer.is_cpu_sequencer = False
+        self.ruby_system = ruby_system
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+class TCC(RubyCache):
+    size = MemorySize("256kB")
+    assoc = 16
+    dataAccessLatency = 8
+    tagAccessLatency = 2
+    resourceStalls = True
+    def create(self, options):
+        self.assoc = options.tcc_assoc
+        if hasattr(options, 'bw_scalor') and options.bw_scalor > 0:
+          s = options.num_compute_units
+          tcc_size = s * 128
+          tcc_size = str(tcc_size)+'kB'
+          self.size = MemorySize(tcc_size)
+          self.dataArrayBanks = 64
+          self.tagArrayBanks = 64
+        else:
+          self.size = MemorySize(options.tcc_size)
+          self.dataArrayBanks = 256 / options.num_tccs #number of data banks
+          self.tagArrayBanks = 256 / options.num_tccs #number of tag banks
+        self.size.value = self.size.value / options.num_tccs
+        if ((self.size.value / long(self.assoc)) < 128):
+            self.size.value = long(128 * self.assoc)
+        self.start_index_bit = math.log(options.cacheline_size, 2) + \
+                               math.log(options.num_tccs, 2)
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+class TCCCntrl(TCC_Controller, CntrlBase):
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+        self.L2cache = TCC()
+        self.L2cache.create(options)
+        self.ruby_system = ruby_system
+        self.L2cache.resourceStalls = options.no_tcc_resource_stalls
+
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+class L3Cache(RubyCache):
+    dataArrayBanks = 16
+    tagArrayBanks = 16
+
+    def create(self, options, ruby_system, system):
+        self.size = MemorySize(options.l3_size)
+        self.size.value /= options.num_dirs
+        self.assoc = options.l3_assoc
+        self.dataArrayBanks /= options.num_dirs
+        self.tagArrayBanks /= options.num_dirs
+        self.dataArrayBanks /= options.num_dirs
+        self.tagArrayBanks /= options.num_dirs
+        self.dataAccessLatency = options.l3_data_latency
+        self.tagAccessLatency = options.l3_tag_latency
+        self.resourceStalls = False
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+class ProbeFilter(RubyCache):
+    size = "4MB"
+    assoc = 16
+    dataArrayBanks = 256
+    tagArrayBanks = 256
+
+    def create(self, options, ruby_system, system):
+        self.block_size = "%dB" % (64 * options.blocks_per_region)
+        self.size = options.region_dir_entries * \
+            self.block_size * options.num_compute_units
+        self.assoc = 8
+        self.tagArrayBanks = 8
+        self.tagAccessLatency = options.dir_tag_latency
+        self.dataAccessLatency = 1
+        self.resourceStalls = options.no_resource_stalls
+        self.start_index_bit = 6 + int(math.log(options.blocks_per_region, 2))
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+class L3Cntrl(L3Cache_Controller, CntrlBase):
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+        self.L3cache = L3Cache()
+        self.L3cache.create(options, ruby_system, system)
+        self.l3_response_latency = \
+            max(self.L3cache.dataAccessLatency, self.L3cache.tagAccessLatency)
+        self.ruby_system = ruby_system
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+    def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir,
+                           req_to_l3, probe_to_l3, resp_to_l3):
+        self.reqToDir = req_to_dir
+        self.respToDir = resp_to_dir
+        self.l3UnblockToDir = l3_unblock_to_dir
+        self.reqToL3 = req_to_l3
+        self.probeToL3 = probe_to_l3
+        self.respToL3 = resp_to_l3
+
+class DirMem(RubyDirectoryMemory, CntrlBase):
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+
+        phys_mem_size = AddrRange(options.mem_size).size()
+        mem_module_size = phys_mem_size / options.num_dirs
+        dir_size = MemorySize('0B')
+        dir_size.value = mem_module_size
+        self.size = dir_size
+
+class DirCntrl(Directory_Controller, CntrlBase):
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+        self.response_latency = 30
+        self.directory = DirMem()
+        self.directory.create(options, ruby_system, system)
+        self.L3CacheMemory = L3Cache()
+        self.L3CacheMemory.create(options, ruby_system, system)
+        self.ProbeFilterMemory = ProbeFilter()
+        self.ProbeFilterMemory.create(options, ruby_system, system)
+        self.l3_hit_latency = \
+            max(self.L3CacheMemory.dataAccessLatency,
+            self.L3CacheMemory.tagAccessLatency)
+
+        self.ruby_system = ruby_system
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+    def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir,
+                           req_to_l3, probe_to_l3, resp_to_l3):
+        self.reqToDir = req_to_dir
+        self.respToDir = resp_to_dir
+        self.l3UnblockToDir = l3_unblock_to_dir
+        self.reqToL3 = req_to_l3
+        self.probeToL3 = probe_to_l3
+        self.respToL3 = resp_to_l3
+
+def define_options(parser):
+    parser.add_option("--num-subcaches", type = "int", default = 4)
+    parser.add_option("--l3-data-latency", type = "int", default = 20)
+    parser.add_option("--l3-tag-latency", type = "int", default = 15)
+    parser.add_option("--cpu-to-dir-latency", type = "int", default = 120)
+    parser.add_option("--gpu-to-dir-latency", type = "int", default = 120)
+    parser.add_option("--no-resource-stalls", action = "store_false",
+                      default = True)
+    parser.add_option("--no-tcc-resource-stalls", action = "store_false",
+                      default = True)
+    parser.add_option("--num-tbes", type = "int", default = 2560)
+    parser.add_option("--l2-latency", type = "int", default = 50)  # load to use
+    parser.add_option("--num-tccs", type = "int", default = 1,
+                      help = "number of TCC banks in the GPU")
+    parser.add_option("--sqc-size", type = 'string', default = '32kB',
+                      help = "SQC cache size")
+    parser.add_option("--sqc-assoc", type = 'int', default = 8,
+                      help = "SQC cache assoc")
+    parser.add_option("--region-dir-entries", type = "int", default = 8192)
+    parser.add_option("--dir-tag-latency", type = "int", default = 8)
+    parser.add_option("--dir-tag-banks", type = "int", default = 4)
+    parser.add_option("--blocks-per-region", type = "int", default = 1)
+    parser.add_option("--use-L3-on-WT", action = "store_true", default = False)
+    parser.add_option("--nonInclusiveDir", action = "store_true",
+                      default = False)
+    parser.add_option("--WB_L1", action = "store_true",
+        default = False, help = "writeback L2")
+    parser.add_option("--WB_L2", action = "store_true",
+        default = False, help = "writeback L2")
+    parser.add_option("--TCP_latency", type = "int",
+        default = 4, help = "TCP latency")
+    parser.add_option("--TCC_latency", type = "int",
+        default = 16, help = "TCC latency")
+    parser.add_option("--tcc-size", type = 'string', default = '2MB',
+                      help = "agregate tcc size")
+    parser.add_option("--tcc-assoc", type = 'int', default = 16,
+                      help = "tcc assoc")
+    parser.add_option("--tcp-size", type = 'string', default = '16kB',
+                      help = "tcp size")
+    parser.add_option("--sampler-sets", type = "int", default = 1024)
+    parser.add_option("--sampler-assoc", type = "int", default = 16)
+    parser.add_option("--sampler-counter", type = "int", default = 512)
+    parser.add_option("--noL1", action = "store_true", default = False,
+                      help = "bypassL1")
+    parser.add_option("--noL2", action = "store_true", default = False,
+                      help = "bypassL2")
+
+def create_system(options, full_system, system, dma_devices, ruby_system):
+    if buildEnv['PROTOCOL'] != 'GPU_VIPER_Baseline':
+        panic("This script requires the" \
+        "GPU_VIPER_Baseline protocol to be built.")
+
+    cpu_sequencers = []
+
+    #
+    # The ruby network creation expects the list of nodes in the system to be
+    # consistent with the NetDest list.  Therefore the l1 controller nodes
+    # must be listed before the directory nodes and directory nodes before
+    # dma nodes, etc.
+    #
+    cp_cntrl_nodes = []
+    tcp_cntrl_nodes = []
+    sqc_cntrl_nodes = []
+    tcc_cntrl_nodes = []
+    dir_cntrl_nodes = []
+    l3_cntrl_nodes = []
+
+    #
+    # Must create the individual controllers before the network to ensure the
+    # controller constructors are called before the network constructor
+    #
+
+    # For an odd number of CPUs, still create the right number of controllers
+    TCC_bits = int(math.log(options.num_tccs, 2))
+
+    # This is the base crossbar that connects the L3s, Dirs, and cpu/gpu
+    # Clusters
+    crossbar_bw = 16 * options.num_compute_units #Assuming a 2GHz clock
+    mainCluster = Cluster(intBW = crossbar_bw)
+    for i in xrange(options.num_dirs):
+
+        dir_cntrl = DirCntrl(noTCCdir=True,TCC_select_num_bits = TCC_bits)
+        dir_cntrl.create(options, ruby_system, system)
+        dir_cntrl.number_of_TBEs = options.num_tbes
+        dir_cntrl.useL3OnWT = options.use_L3_on_WT
+        dir_cntrl.inclusiveDir = not options.nonInclusiveDir
+
+        # Connect the Directory controller to the ruby network
+        dir_cntrl.requestFromCores = MessageBuffer(ordered = True)
+        dir_cntrl.requestFromCores.slave = ruby_system.network.master
+
+        dir_cntrl.responseFromCores = MessageBuffer()
+        dir_cntrl.responseFromCores.slave = ruby_system.network.master
+
+        dir_cntrl.unblockFromCores = MessageBuffer()
+        dir_cntrl.unblockFromCores.slave = ruby_system.network.master
+
+        dir_cntrl.probeToCore = MessageBuffer()
+        dir_cntrl.probeToCore.master = ruby_system.network.slave
+
+        dir_cntrl.responseToCore = MessageBuffer()
+        dir_cntrl.responseToCore.master = ruby_system.network.slave
+
+        dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
+        dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True)
+        dir_cntrl.responseFromMemory = MessageBuffer()
+
+        exec("system.dir_cntrl%d = dir_cntrl" % i)
+        dir_cntrl_nodes.append(dir_cntrl)
+        mainCluster.add(dir_cntrl)
+
+    cpuCluster = Cluster(extBW = crossbar_bw, intBW=crossbar_bw)
+    for i in xrange((options.num_cpus + 1) / 2):
+
+        cp_cntrl = CPCntrl()
+        cp_cntrl.create(options, ruby_system, system)
+
+        exec("system.cp_cntrl%d = cp_cntrl" % i)
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1])
+
+        # Connect the CP controllers and the network
+        cp_cntrl.requestFromCore = MessageBuffer()
+        cp_cntrl.requestFromCore.master = ruby_system.network.slave
+
+        cp_cntrl.responseFromCore = MessageBuffer()
+        cp_cntrl.responseFromCore.master = ruby_system.network.slave
+
+        cp_cntrl.unblockFromCore = MessageBuffer()
+        cp_cntrl.unblockFromCore.master = ruby_system.network.slave
+
+        cp_cntrl.probeToCore = MessageBuffer()
+        cp_cntrl.probeToCore.slave = ruby_system.network.master
+
+        cp_cntrl.responseToCore = MessageBuffer()
+        cp_cntrl.responseToCore.slave = ruby_system.network.master
+
+        cp_cntrl.mandatoryQueue = MessageBuffer()
+        cp_cntrl.triggerQueue = MessageBuffer(ordered = True)
+
+        cpuCluster.add(cp_cntrl)
+
+    gpuCluster = Cluster(extBW = crossbar_bw, intBW = crossbar_bw)
+    for i in xrange(options.num_compute_units):
+
+        tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits,
+                             issue_latency = 1,
+                             number_of_TBEs = 2560)
+        # TBEs set to max outstanding requests
+        tcp_cntrl.create(options, ruby_system, system)
+        tcp_cntrl.WB = options.WB_L1
+        tcp_cntrl.disableL1 = options.noL1
+
+        exec("system.tcp_cntrl%d = tcp_cntrl" % i)
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.append(tcp_cntrl.coalescer)
+        tcp_cntrl_nodes.append(tcp_cntrl)
+
+        # Connect the CP (TCP) controllers to the ruby network
+        tcp_cntrl.requestFromTCP = MessageBuffer(ordered = True)
+        tcp_cntrl.requestFromTCP.master = ruby_system.network.slave
+
+        tcp_cntrl.responseFromTCP = MessageBuffer(ordered = True)
+        tcp_cntrl.responseFromTCP.master = ruby_system.network.slave
+
+        tcp_cntrl.unblockFromCore = MessageBuffer()
+        tcp_cntrl.unblockFromCore.master = ruby_system.network.slave
+
+        tcp_cntrl.probeToTCP = MessageBuffer(ordered = True)
+        tcp_cntrl.probeToTCP.slave = ruby_system.network.master
+
+        tcp_cntrl.responseToTCP = MessageBuffer(ordered = True)
+        tcp_cntrl.responseToTCP.slave = ruby_system.network.master
+
+        tcp_cntrl.mandatoryQueue = MessageBuffer()
+
+        gpuCluster.add(tcp_cntrl)
+
+    for i in xrange(options.num_sqc):
+
+        sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits)
+        sqc_cntrl.create(options, ruby_system, system)
+
+        exec("system.sqc_cntrl%d = sqc_cntrl" % i)
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.append(sqc_cntrl.sequencer)
+
+        # Connect the SQC controller to the ruby network
+        sqc_cntrl.requestFromSQC = MessageBuffer(ordered = True)
+        sqc_cntrl.requestFromSQC.master = ruby_system.network.slave
+
+        sqc_cntrl.probeToSQC = MessageBuffer(ordered = True)
+        sqc_cntrl.probeToSQC.slave = ruby_system.network.master
+
+        sqc_cntrl.responseToSQC = MessageBuffer(ordered = True)
+        sqc_cntrl.responseToSQC.slave = ruby_system.network.master
+
+        sqc_cntrl.mandatoryQueue = MessageBuffer()
+
+        # SQC also in GPU cluster
+        gpuCluster.add(sqc_cntrl)
+
+    # Because of wire buffers, num_tccs must equal num_tccdirs
+    numa_bit = 6
+
+    for i in xrange(options.num_tccs):
+
+        tcc_cntrl = TCCCntrl()
+        tcc_cntrl.create(options, ruby_system, system)
+        tcc_cntrl.l2_request_latency = options.gpu_to_dir_latency
+        tcc_cntrl.l2_response_latency = options.TCC_latency
+        tcc_cntrl_nodes.append(tcc_cntrl)
+        tcc_cntrl.WB = options.WB_L2
+        tcc_cntrl.number_of_TBEs = 2560 * options.num_compute_units
+
+        # Connect the TCC controllers to the ruby network
+        tcc_cntrl.requestFromTCP = MessageBuffer(ordered = True)
+        tcc_cntrl.requestFromTCP.slave = ruby_system.network.master
+
+        tcc_cntrl.responseToCore = MessageBuffer(ordered = True)
+        tcc_cntrl.responseToCore.master = ruby_system.network.slave
+
+        tcc_cntrl.probeFromNB = MessageBuffer()
+        tcc_cntrl.probeFromNB.slave = ruby_system.network.master
+
+        tcc_cntrl.responseFromNB = MessageBuffer()
+        tcc_cntrl.responseFromNB.slave = ruby_system.network.master
+
+        tcc_cntrl.requestToNB = MessageBuffer(ordered = True)
+        tcc_cntrl.requestToNB.master = ruby_system.network.slave
+
+        tcc_cntrl.responseToNB = MessageBuffer()
+        tcc_cntrl.responseToNB.master = ruby_system.network.slave
+
+        tcc_cntrl.unblockToNB = MessageBuffer()
+        tcc_cntrl.unblockToNB.master = ruby_system.network.slave
+
+        tcc_cntrl.triggerQueue = MessageBuffer(ordered = True)
+
+        exec("system.tcc_cntrl%d = tcc_cntrl" % i)
+        # connect all of the wire buffers between L3 and dirs up
+        # TCC cntrls added to the GPU cluster
+        gpuCluster.add(tcc_cntrl)
+
+    # Assuming no DMA devices
+    assert(len(dma_devices) == 0)
+
+    # Add cpu/gpu clusters to main cluster
+    mainCluster.add(cpuCluster)
+    mainCluster.add(gpuCluster)
+
+    ruby_system.network.number_of_virtual_networks = 10
+
+    return (cpu_sequencers, dir_cntrl_nodes, mainCluster)
diff --git a/configs/ruby/GPU_VIPER_Region.py b/configs/ruby/GPU_VIPER_Region.py
new file mode 100644
index 000000000..94cb9b70b
--- /dev/null
+++ b/configs/ruby/GPU_VIPER_Region.py
@@ -0,0 +1,758 @@
+#
+#  Copyright (c) 2015 Advanced Micro Devices, Inc.
+#  All rights reserved.
+#
+#  For use for simulation and test purposes only
+#
+#  Redistribution and use in source and binary forms, with or without
+#  modification, are permitted provided that the following conditions are met:
+#
+#  1. Redistributions of source code must retain the above copyright notice,
+#  this list of conditions and the following disclaimer.
+#
+#  2. Redistributions in binary form must reproduce the above copyright notice,
+#  this list of conditions and the following disclaimer in the documentation
+#  and/or other materials provided with the distribution.
+#
+#  3. Neither the name of the copyright holder nor the names of its contributors
+#  may be used to endorse or promote products derived from this software
+#  without specific prior written permission.
+#
+#  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+#  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+#  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+#  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+#  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+#  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+#  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+#  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+#  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+#  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+#  POSSIBILITY OF SUCH DAMAGE.
+#
+#  Author: Sooraj Puthoor
+#
+
+import math
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+from Ruby import send_evicts
+
+from Cluster import Cluster
+
+class CntrlBase:
+    _seqs = 0
+    @classmethod
+    def seqCount(cls):
+        # Use SeqCount not class since we need global count
+        CntrlBase._seqs += 1
+        return CntrlBase._seqs - 1
+
+    _cntrls = 0
+    @classmethod
+    def cntrlCount(cls):
+        # Use CntlCount not class since we need global count
+        CntrlBase._cntrls += 1
+        return CntrlBase._cntrls - 1
+
+    _version = 0
+    @classmethod
+    def versionCount(cls):
+        cls._version += 1 # Use count for this particular type
+        return cls._version - 1
+
+#
+# Note: the L1 Cache latency is only used by the sequencer on fast path hits
+#
+class L1Cache(RubyCache):
+    resourceStalls = False
+    dataArrayBanks = 2
+    tagArrayBanks = 2
+    dataAccessLatency = 1
+    tagAccessLatency = 1
+    def create(self, size, assoc, options):
+        self.size = MemorySize(size)
+        self.assoc = assoc
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+class L2Cache(RubyCache):
+    resourceStalls = False
+    assoc = 16
+    dataArrayBanks = 16
+    tagArrayBanks = 16
+    def create(self, size, assoc, options):
+        self.size = MemorySize(size)
+        self.assoc = assoc
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+class CPCntrl(CorePair_Controller, CntrlBase):
+
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+
+        self.L1Icache = L1Cache()
+        self.L1Icache.create(options.l1i_size, options.l1i_assoc, options)
+        self.L1D0cache = L1Cache()
+        self.L1D0cache.create(options.l1d_size, options.l1d_assoc, options)
+        self.L1D1cache = L1Cache()
+        self.L1D1cache.create(options.l1d_size, options.l1d_assoc, options)
+        self.L2cache = L2Cache()
+        self.L2cache.create(options.l2_size, options.l2_assoc, options)
+
+        self.sequencer = RubySequencer()
+        self.sequencer.version = self.seqCount()
+        self.sequencer.icache = self.L1Icache
+        self.sequencer.dcache = self.L1D0cache
+        self.sequencer.ruby_system = ruby_system
+        self.sequencer.coreid = 0
+        self.sequencer.is_cpu_sequencer = True
+
+        self.sequencer1 = RubySequencer()
+        self.sequencer1.version = self.seqCount()
+        self.sequencer1.icache = self.L1Icache
+        self.sequencer1.dcache = self.L1D1cache
+        self.sequencer1.ruby_system = ruby_system
+        self.sequencer1.coreid = 1
+        self.sequencer1.is_cpu_sequencer = True
+
+        self.issue_latency = 1
+        self.send_evictions = send_evicts(options)
+
+        self.ruby_system = ruby_system
+
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+class TCPCache(RubyCache):
+    size = "16kB"
+    assoc = 16
+    dataArrayBanks = 16
+    tagArrayBanks = 16
+    dataAccessLatency = 4
+    tagAccessLatency = 1
+    def create(self, options):
+        self.size = MemorySize(options.tcp_size)
+        self.dataArrayBanks = 16
+        self.tagArrayBanks = 16
+        self.dataAccessLatency = 4
+        self.tagAccessLatency = 1
+        self.resourceStalls = options.no_tcc_resource_stalls
+        self.replacement_policy = PseudoLRUReplacementPolicy(assoc = self.assoc)
+
+class TCPCntrl(TCP_Controller, CntrlBase):
+
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+        self.L1cache = TCPCache(dataAccessLatency = options.TCP_latency)
+        self.L1cache.create(options)
+        self.issue_latency = 1
+
+        self.coalescer = VIPERCoalescer()
+        self.coalescer.version = self.seqCount()
+        self.coalescer.icache = self.L1cache
+        self.coalescer.dcache = self.L1cache
+        self.coalescer.ruby_system = ruby_system
+        self.coalescer.support_inst_reqs = False
+        self.coalescer.is_cpu_sequencer = False
+
+        self.sequencer = RubySequencer()
+        self.sequencer.version = self.seqCount()
+        self.sequencer.icache = self.L1cache
+        self.sequencer.dcache = self.L1cache
+        self.sequencer.ruby_system = ruby_system
+        self.sequencer.is_cpu_sequencer = True
+
+        self.use_seq_not_coal = False
+
+        self.ruby_system = ruby_system
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+class SQCCache(RubyCache):
+    dataArrayBanks = 8
+    tagArrayBanks = 8
+    dataAccessLatency = 1
+    tagAccessLatency = 1
+
+    def create(self, options):
+        self.size = MemorySize(options.sqc_size)
+        self.assoc = options.sqc_assoc
+        self.replacement_policy = PseudoLRUReplacementPolicy(assoc = self.assoc)
+
+class SQCCntrl(SQC_Controller, CntrlBase):
+
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+        self.L1cache = SQCCache()
+        self.L1cache.create(options)
+        self.L1cache.resourceStalls = False
+        self.sequencer = RubySequencer()
+        self.sequencer.version = self.seqCount()
+        self.sequencer.icache = self.L1cache
+        self.sequencer.dcache = self.L1cache
+        self.sequencer.ruby_system = ruby_system
+        self.sequencer.support_data_reqs = False
+        self.sequencer.is_cpu_sequencer = False
+        self.ruby_system = ruby_system
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+class TCC(RubyCache):
+    size = MemorySize("256kB")
+    assoc = 16
+    dataAccessLatency = 8
+    tagAccessLatency = 2
+    resourceStalls = False
+    def create(self, options):
+        self.assoc = options.tcc_assoc
+        if hasattr(options, 'bw_scalor') and options.bw_scalor > 0:
+          s = options.num_compute_units
+          tcc_size = s * 128
+          tcc_size = str(tcc_size)+'kB'
+          self.size = MemorySize(tcc_size)
+          self.dataArrayBanks = 64
+          self.tagArrayBanks = 64
+        else:
+          self.size = MemorySize(options.tcc_size)
+          self.dataArrayBanks = 256 / options.num_tccs #number of data banks
+          self.tagArrayBanks = 256 / options.num_tccs #number of tag banks
+        self.size.value = self.size.value / options.num_tccs
+        if ((self.size.value / long(self.assoc)) < 128):
+            self.size.value = long(128 * self.assoc)
+        self.start_index_bit = math.log(options.cacheline_size, 2) + \
+                               math.log(options.num_tccs, 2)
+        self.replacement_policy = PseudoLRUReplacementPolicy(assoc = self.assoc)
+
+class TCCCntrl(TCC_Controller, CntrlBase):
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+        self.L2cache = TCC()
+        self.L2cache.create(options)
+        self.ruby_system = ruby_system
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+class L3Cache(RubyCache):
+    dataArrayBanks = 16
+    tagArrayBanks = 16
+
+    def create(self, options, ruby_system, system):
+        self.size = MemorySize(options.l3_size)
+        self.size.value /= options.num_dirs
+        self.assoc = options.l3_assoc
+        self.dataArrayBanks /= options.num_dirs
+        self.tagArrayBanks /= options.num_dirs
+        self.dataArrayBanks /= options.num_dirs
+        self.tagArrayBanks /= options.num_dirs
+        self.dataAccessLatency = options.l3_data_latency
+        self.tagAccessLatency = options.l3_tag_latency
+        self.resourceStalls = False
+        self.replacement_policy = PseudoLRUReplacementPolicy(assoc = self.assoc)
+
+class L3Cntrl(L3Cache_Controller, CntrlBase):
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+        self.L3cache = L3Cache()
+        self.L3cache.create(options, ruby_system, system)
+        self.l3_response_latency = \
+            max(self.L3cache.dataAccessLatency, self.L3cache.tagAccessLatency)
+        self.ruby_system = ruby_system
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+    def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir,
+                           req_to_l3, probe_to_l3, resp_to_l3):
+        self.reqToDir = req_to_dir
+        self.respToDir = resp_to_dir
+        self.l3UnblockToDir = l3_unblock_to_dir
+        self.reqToL3 = req_to_l3
+        self.probeToL3 = probe_to_l3
+        self.respToL3 = resp_to_l3
+
+# Directory memory: Directory memory of infinite size which is
+# used by directory controller to store the "states" of the
+# state machine. The state machine is implemented per cache block
+class DirMem(RubyDirectoryMemory, CntrlBase):
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+        phys_mem_size = AddrRange(options.mem_size).size()
+        mem_module_size = phys_mem_size / options.num_dirs
+        dir_size = MemorySize('0B')
+        dir_size.value = mem_module_size
+        self.size = dir_size
+
+# Directory controller: Contains directory memory, L3 cache and associated state
+# machine which is used to accurately redirect a data request to L3 cache or to
+# memory. The permissions requests do not come to this directory for region
+# based protocols as they are handled exclusively by the region directory.
+# However, region directory controller uses this directory controller for
+# sending probe requests and receiving probe responses.
+class DirCntrl(Directory_Controller, CntrlBase):
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+        self.response_latency = 25
+        self.response_latency_regionDir = 1
+        self.directory = DirMem()
+        self.directory.create(options, ruby_system, system)
+        self.L3CacheMemory = L3Cache()
+        self.L3CacheMemory.create(options, ruby_system, system)
+        self.l3_hit_latency = \
+            max(self.L3CacheMemory.dataAccessLatency,
+            self.L3CacheMemory.tagAccessLatency)
+
+        self.ruby_system = ruby_system
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+    def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir,
+                           req_to_l3, probe_to_l3, resp_to_l3):
+        self.reqToDir = req_to_dir
+        self.respToDir = resp_to_dir
+        self.l3UnblockToDir = l3_unblock_to_dir
+        self.reqToL3 = req_to_l3
+        self.probeToL3 = probe_to_l3
+        self.respToL3 = resp_to_l3
+
+# Region directory : Stores region permissions
+class RegionDir(RubyCache):
+
+    def create(self, options, ruby_system, system):
+        self.block_size = "%dB" % (64 * options.blocks_per_region)
+        self.size = options.region_dir_entries * \
+            self.block_size * options.num_compute_units
+        self.assoc = 8
+        self.tagArrayBanks = 8
+        self.tagAccessLatency = options.dir_tag_latency
+        self.dataAccessLatency = 1
+        self.resourceStalls = options.no_resource_stalls
+        self.start_index_bit = 6 + int(math.log(options.blocks_per_region, 2))
+        self.replacement_policy = PseudoLRUReplacementPolicy(assoc = self.assoc)
+# Region directory controller : Contains region directory and associated state
+# machine for dealing with region coherence requests.
+class RegionCntrl(RegionDir_Controller, CntrlBase):
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+        self.cacheMemory = RegionDir()
+        self.cacheMemory.create(options, ruby_system, system)
+        self.blocksPerRegion = options.blocks_per_region
+        self.toDirLatency = \
+            max(self.cacheMemory.dataAccessLatency,
+            self.cacheMemory.tagAccessLatency)
+        self.ruby_system = ruby_system
+        self.always_migrate = options.always_migrate
+        self.sym_migrate = options.symmetric_migrate
+        self.asym_migrate = options.asymmetric_migrate
+        if self.always_migrate:
+            assert(not self.asym_migrate and not self.sym_migrate)
+        if self.sym_migrate:
+            assert(not self.always_migrate and not self.asym_migrate)
+        if self.asym_migrate:
+            assert(not self.always_migrate and not self.sym_migrate)
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+# Region Buffer: A region directory cache which avoids some potential
+# long latency lookup of region directory for getting region permissions
+class RegionBuffer(RubyCache):
+    assoc = 4
+    dataArrayBanks = 256
+    tagArrayBanks = 256
+    dataAccessLatency = 1
+    tagAccessLatency = 1
+    resourceStalls = True
+
+class RBCntrl(RegionBuffer_Controller, CntrlBase):
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+        self.cacheMemory = RegionBuffer()
+        self.cacheMemory.resourceStalls = options.no_tcc_resource_stalls
+        self.cacheMemory.dataArrayBanks = 64
+        self.cacheMemory.tagArrayBanks = 64
+        self.blocksPerRegion = options.blocks_per_region
+        self.cacheMemory.block_size = "%dB" % (64 * self.blocksPerRegion)
+        self.cacheMemory.start_index_bit = \
+            6 + int(math.log(self.blocksPerRegion, 2))
+        self.cacheMemory.size = options.region_buffer_entries * \
+            self.cacheMemory.block_size * options.num_compute_units
+        self.toDirLatency = options.gpu_to_dir_latency
+        self.toRegionDirLatency = options.cpu_to_dir_latency
+        self.noTCCdir = True
+        TCC_bits = int(math.log(options.num_tccs, 2))
+        self.TCC_select_num_bits = TCC_bits
+        self.ruby_system = ruby_system
+
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+        self.cacheMemory.replacement_policy = \
+            PseudoLRUReplacementPolicy(assoc = self.cacheMemory.assoc)
+
+def define_options(parser):
+    parser.add_option("--num-subcaches", type="int", default=4)
+    parser.add_option("--l3-data-latency", type="int", default=20)
+    parser.add_option("--l3-tag-latency", type="int", default=15)
+    parser.add_option("--cpu-to-dir-latency", type="int", default=120)
+    parser.add_option("--gpu-to-dir-latency", type="int", default=60)
+    parser.add_option("--no-resource-stalls", action="store_false",
+                      default=True)
+    parser.add_option("--no-tcc-resource-stalls", action="store_false",
+                      default=True)
+    parser.add_option("--num-tbes", type="int", default=32)
+    parser.add_option("--l2-latency", type="int", default=50) # load to use
+    parser.add_option("--num-tccs", type="int", default=1,
+                      help="number of TCC banks in the GPU")
+
+    parser.add_option("--sqc-size", type='string', default='32kB',
+                      help="SQC cache size")
+    parser.add_option("--sqc-assoc", type='int', default=8,
+                      help="SQC cache assoc")
+
+    parser.add_option("--WB_L1", action="store_true",
+        default=False, help="L2 Writeback Cache")
+    parser.add_option("--WB_L2", action="store_true",
+        default=False, help="L2 Writeback Cache")
+    parser.add_option("--TCP_latency",
+        type="int", default=4, help="TCP latency")
+    parser.add_option("--TCC_latency",
+        type="int", default=16, help="TCC latency")
+    parser.add_option("--tcc-size", type='string', default='2MB',
+                      help="agregate tcc size")
+    parser.add_option("--tcc-assoc", type='int', default=16,
+                      help="tcc assoc")
+    parser.add_option("--tcp-size", type='string', default='16kB',
+                      help="tcp size")
+
+    parser.add_option("--dir-tag-latency", type="int", default=4)
+    parser.add_option("--dir-tag-banks", type="int", default=4)
+    parser.add_option("--blocks-per-region", type="int", default=16)
+    parser.add_option("--dir-entries", type="int", default=8192)
+
+    # Region buffer is a cache of region directory. Hence region
+    # directory is inclusive with respect to region directory.
+    # However, region directory is non-inclusive with respect to
+    # the caches in the system
+    parser.add_option("--region-dir-entries", type="int", default=1024)
+    parser.add_option("--region-buffer-entries", type="int", default=512)
+
+    parser.add_option("--always-migrate",
+        action="store_true", default=False)
+    parser.add_option("--symmetric-migrate",
+        action="store_true", default=False)
+    parser.add_option("--asymmetric-migrate",
+        action="store_true", default=False)
+    parser.add_option("--use-L3-on-WT", action="store_true", default=False)
+
+def create_system(options, full_system, system, dma_devices, ruby_system):
+    if buildEnv['PROTOCOL'] != 'GPU_VIPER_Region':
+        panic("This script requires the GPU_VIPER_Region protocol to be built.")
+
+    cpu_sequencers = []
+
+    #
+    # The ruby network creation expects the list of nodes in the system to be
+    # consistent with the NetDest list.  Therefore the l1 controller nodes
+    # must be listed before the directory nodes and directory nodes before
+    # dma nodes, etc.
+    #
+    dir_cntrl_nodes = []
+
+    # For an odd number of CPUs, still create the right number of controllers
+    TCC_bits = int(math.log(options.num_tccs, 2))
+
+    #
+    # Must create the individual controllers before the network to ensure the
+    # controller constructors are called before the network constructor
+    #
+
+    # For an odd number of CPUs, still create the right number of controllers
+    crossbar_bw = 16 * options.num_compute_units #Assuming a 2GHz clock
+    cpuCluster = Cluster(extBW = (crossbar_bw), intBW=crossbar_bw)
+    for i in xrange((options.num_cpus + 1) / 2):
+
+        cp_cntrl = CPCntrl()
+        cp_cntrl.create(options, ruby_system, system)
+
+        rb_cntrl = RBCntrl()
+        rb_cntrl.create(options, ruby_system, system)
+        rb_cntrl.number_of_TBEs = 256
+        rb_cntrl.isOnCPU = True
+
+        cp_cntrl.regionBufferNum = rb_cntrl.version
+
+        exec("system.cp_cntrl%d = cp_cntrl" % i)
+        exec("system.rb_cntrl%d = rb_cntrl" % i)
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1])
+
+        # Connect the CP controllers and the network
+        cp_cntrl.requestFromCore = MessageBuffer()
+        cp_cntrl.requestFromCore.master = ruby_system.network.slave
+
+        cp_cntrl.responseFromCore = MessageBuffer()
+        cp_cntrl.responseFromCore.master = ruby_system.network.slave
+
+        cp_cntrl.unblockFromCore = MessageBuffer()
+        cp_cntrl.unblockFromCore.master = ruby_system.network.slave
+
+        cp_cntrl.probeToCore = MessageBuffer()
+        cp_cntrl.probeToCore.slave = ruby_system.network.master
+
+        cp_cntrl.responseToCore = MessageBuffer()
+        cp_cntrl.responseToCore.slave = ruby_system.network.master
+
+        cp_cntrl.mandatoryQueue = MessageBuffer()
+        cp_cntrl.triggerQueue = MessageBuffer(ordered = True)
+
+        # Connect the RB controllers to the ruby network
+        rb_cntrl.requestFromCore = MessageBuffer(ordered = True)
+        rb_cntrl.requestFromCore.slave = ruby_system.network.master
+
+        rb_cntrl.responseFromCore = MessageBuffer()
+        rb_cntrl.responseFromCore.slave = ruby_system.network.master
+
+        rb_cntrl.requestToNetwork = MessageBuffer()
+        rb_cntrl.requestToNetwork.master = ruby_system.network.slave
+
+        rb_cntrl.notifyFromRegionDir = MessageBuffer()
+        rb_cntrl.notifyFromRegionDir.slave = ruby_system.network.master
+
+        rb_cntrl.probeFromRegionDir = MessageBuffer()
+        rb_cntrl.probeFromRegionDir.slave = ruby_system.network.master
+
+        rb_cntrl.unblockFromDir = MessageBuffer()
+        rb_cntrl.unblockFromDir.slave = ruby_system.network.master
+
+        rb_cntrl.responseToRegDir = MessageBuffer()
+        rb_cntrl.responseToRegDir.master = ruby_system.network.slave
+
+        rb_cntrl.triggerQueue = MessageBuffer(ordered = True)
+
+        cpuCluster.add(cp_cntrl)
+        cpuCluster.add(rb_cntrl)
+
+    gpuCluster = Cluster(extBW = (crossbar_bw), intBW = crossbar_bw)
+    for i in xrange(options.num_compute_units):
+
+        tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits,
+                             issue_latency = 1,
+                             number_of_TBEs = 2560)
+        # TBEs set to max outstanding requests
+        tcp_cntrl.create(options, ruby_system, system)
+        tcp_cntrl.WB = options.WB_L1
+        tcp_cntrl.disableL1 = False
+
+        exec("system.tcp_cntrl%d = tcp_cntrl" % i)
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.append(tcp_cntrl.coalescer)
+
+        # Connect the CP (TCP) controllers to the ruby network
+        tcp_cntrl.requestFromTCP = MessageBuffer(ordered = True)
+        tcp_cntrl.requestFromTCP.master = ruby_system.network.slave
+
+        tcp_cntrl.responseFromTCP = MessageBuffer(ordered = True)
+        tcp_cntrl.responseFromTCP.master = ruby_system.network.slave
+
+        tcp_cntrl.unblockFromCore = MessageBuffer()
+        tcp_cntrl.unblockFromCore.master = ruby_system.network.slave
+
+        tcp_cntrl.probeToTCP = MessageBuffer(ordered = True)
+        tcp_cntrl.probeToTCP.slave = ruby_system.network.master
+
+        tcp_cntrl.responseToTCP = MessageBuffer(ordered = True)
+        tcp_cntrl.responseToTCP.slave = ruby_system.network.master
+
+        tcp_cntrl.mandatoryQueue = MessageBuffer()
+
+        gpuCluster.add(tcp_cntrl)
+
+    for i in xrange(options.num_sqc):
+
+        sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits)
+        sqc_cntrl.create(options, ruby_system, system)
+
+        exec("system.sqc_cntrl%d = sqc_cntrl" % i)
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.append(sqc_cntrl.sequencer)
+
+        # Connect the SQC controller to the ruby network
+        sqc_cntrl.requestFromSQC = MessageBuffer(ordered = True)
+        sqc_cntrl.requestFromSQC.master = ruby_system.network.slave
+
+        sqc_cntrl.probeToSQC = MessageBuffer(ordered = True)
+        sqc_cntrl.probeToSQC.slave = ruby_system.network.master
+
+        sqc_cntrl.responseToSQC = MessageBuffer(ordered = True)
+        sqc_cntrl.responseToSQC.slave = ruby_system.network.master
+
+        sqc_cntrl.mandatoryQueue = MessageBuffer()
+
+        # SQC also in GPU cluster
+        gpuCluster.add(sqc_cntrl)
+
+    numa_bit = 6
+
+    for i in xrange(options.num_tccs):
+
+        tcc_cntrl = TCCCntrl()
+        tcc_cntrl.create(options, ruby_system, system)
+        tcc_cntrl.l2_request_latency = 1
+        tcc_cntrl.l2_response_latency = options.TCC_latency
+        tcc_cntrl.WB = options.WB_L2
+        tcc_cntrl.number_of_TBEs = 2560 * options.num_compute_units
+
+        # Connect the TCC controllers to the ruby network
+        tcc_cntrl.requestFromTCP = MessageBuffer(ordered = True)
+        tcc_cntrl.requestFromTCP.slave = ruby_system.network.master
+
+        tcc_cntrl.responseToCore = MessageBuffer(ordered = True)
+        tcc_cntrl.responseToCore.master = ruby_system.network.slave
+
+        tcc_cntrl.probeFromNB = MessageBuffer()
+        tcc_cntrl.probeFromNB.slave = ruby_system.network.master
+
+        tcc_cntrl.responseFromNB = MessageBuffer()
+        tcc_cntrl.responseFromNB.slave = ruby_system.network.master
+
+        tcc_cntrl.requestToNB = MessageBuffer(ordered = True)
+        tcc_cntrl.requestToNB.master = ruby_system.network.slave
+
+        tcc_cntrl.responseToNB = MessageBuffer()
+        tcc_cntrl.responseToNB.master = ruby_system.network.slave
+
+        tcc_cntrl.unblockToNB = MessageBuffer()
+        tcc_cntrl.unblockToNB.master = ruby_system.network.slave
+
+        tcc_cntrl.triggerQueue = MessageBuffer(ordered = True)
+
+        rb_cntrl = RBCntrl()
+        rb_cntrl.create(options, ruby_system, system)
+        rb_cntrl.number_of_TBEs = 2560 * options.num_compute_units
+        rb_cntrl.isOnCPU = False
+
+        # Connect the RB controllers to the ruby network
+        rb_cntrl.requestFromCore = MessageBuffer(ordered = True)
+        rb_cntrl.requestFromCore.slave = ruby_system.network.master
+
+        rb_cntrl.responseFromCore = MessageBuffer()
+        rb_cntrl.responseFromCore.slave = ruby_system.network.master
+
+        rb_cntrl.requestToNetwork = MessageBuffer()
+        rb_cntrl.requestToNetwork.master = ruby_system.network.slave
+
+        rb_cntrl.notifyFromRegionDir = MessageBuffer()
+        rb_cntrl.notifyFromRegionDir.slave = ruby_system.network.master
+
+        rb_cntrl.probeFromRegionDir = MessageBuffer()
+        rb_cntrl.probeFromRegionDir.slave = ruby_system.network.master
+
+        rb_cntrl.unblockFromDir = MessageBuffer()
+        rb_cntrl.unblockFromDir.slave = ruby_system.network.master
+
+        rb_cntrl.responseToRegDir = MessageBuffer()
+        rb_cntrl.responseToRegDir.master = ruby_system.network.slave
+
+        rb_cntrl.triggerQueue = MessageBuffer(ordered = True)
+
+        tcc_cntrl.regionBufferNum = rb_cntrl.version
+
+        exec("system.tcc_cntrl%d = tcc_cntrl" % i)
+        exec("system.tcc_rb_cntrl%d = rb_cntrl" % i)
+
+        # TCC cntrls added to the GPU cluster
+        gpuCluster.add(tcc_cntrl)
+        gpuCluster.add(rb_cntrl)
+
+    # Because of wire buffers, num_l3caches must equal num_dirs
+    # Region coherence only works with 1 dir
+    assert(options.num_l3caches == options.num_dirs == 1)
+
+    # This is the base crossbar that connects the L3s, Dirs, and cpu/gpu
+    # Clusters
+    mainCluster = Cluster(intBW = crossbar_bw)
+
+    dir_cntrl = DirCntrl()
+    dir_cntrl.create(options, ruby_system, system)
+    dir_cntrl.number_of_TBEs = 2560 * options.num_compute_units
+    dir_cntrl.useL3OnWT = options.use_L3_on_WT
+
+    # Connect the Directory controller to the ruby network
+    dir_cntrl.requestFromCores = MessageBuffer()
+    dir_cntrl.requestFromCores.slave = ruby_system.network.master
+
+    dir_cntrl.responseFromCores = MessageBuffer()
+    dir_cntrl.responseFromCores.slave = ruby_system.network.master
+
+    dir_cntrl.unblockFromCores = MessageBuffer()
+    dir_cntrl.unblockFromCores.slave = ruby_system.network.master
+
+    dir_cntrl.probeToCore = MessageBuffer()
+    dir_cntrl.probeToCore.master = ruby_system.network.slave
+
+    dir_cntrl.responseToCore = MessageBuffer()
+    dir_cntrl.responseToCore.master = ruby_system.network.slave
+
+    dir_cntrl.reqFromRegBuf = MessageBuffer()
+    dir_cntrl.reqFromRegBuf.slave = ruby_system.network.master
+
+    dir_cntrl.reqToRegDir = MessageBuffer(ordered = True)
+    dir_cntrl.reqToRegDir.master = ruby_system.network.slave
+
+    dir_cntrl.reqFromRegDir = MessageBuffer(ordered = True)
+    dir_cntrl.reqFromRegDir.slave = ruby_system.network.master
+
+    dir_cntrl.unblockToRegDir = MessageBuffer()
+    dir_cntrl.unblockToRegDir.master = ruby_system.network.slave
+
+    dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
+    dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True)
+    dir_cntrl.responseFromMemory = MessageBuffer()
+
+    exec("system.dir_cntrl%d = dir_cntrl" % i)
+    dir_cntrl_nodes.append(dir_cntrl)
+
+    mainCluster.add(dir_cntrl)
+
+    reg_cntrl = RegionCntrl(noTCCdir=True,TCC_select_num_bits = TCC_bits)
+    reg_cntrl.create(options, ruby_system, system)
+    reg_cntrl.number_of_TBEs = options.num_tbes
+    reg_cntrl.cpuRegionBufferNum = system.rb_cntrl0.version
+    reg_cntrl.gpuRegionBufferNum = system.tcc_rb_cntrl0.version
+
+    # Connect the Region Dir controllers to the ruby network
+    reg_cntrl.requestToDir = MessageBuffer(ordered = True)
+    reg_cntrl.requestToDir.master = ruby_system.network.slave
+
+    reg_cntrl.notifyToRBuffer = MessageBuffer()
+    reg_cntrl.notifyToRBuffer.master = ruby_system.network.slave
+
+    reg_cntrl.probeToRBuffer = MessageBuffer()
+    reg_cntrl.probeToRBuffer.master = ruby_system.network.slave
+
+    reg_cntrl.responseFromRBuffer = MessageBuffer()
+    reg_cntrl.responseFromRBuffer.slave = ruby_system.network.master
+
+    reg_cntrl.requestFromRegBuf = MessageBuffer()
+    reg_cntrl.requestFromRegBuf.slave = ruby_system.network.master
+
+    reg_cntrl.triggerQueue = MessageBuffer(ordered = True)
+
+    exec("system.reg_cntrl%d = reg_cntrl" % i)
+
+    mainCluster.add(reg_cntrl)
+
+    # Assuming no DMA devices
+    assert(len(dma_devices) == 0)
+
+    # Add cpu/gpu clusters to main cluster
+    mainCluster.add(cpuCluster)
+    mainCluster.add(gpuCluster)
+
+    ruby_system.network.number_of_virtual_networks = 10
+
+    return (cpu_sequencers, dir_cntrl_nodes, mainCluster)
diff --git a/configs/ruby/MOESI_AMD_Base.py b/configs/ruby/MOESI_AMD_Base.py
new file mode 100644
index 000000000..4c8ad28b0
--- /dev/null
+++ b/configs/ruby/MOESI_AMD_Base.py
@@ -0,0 +1,326 @@
+#
+#  Copyright (c) 2010-2015 Advanced Micro Devices, Inc.
+#  All rights reserved.
+#
+#  For use for simulation and test purposes only
+#
+#  Redistribution and use in source and binary forms, with or without
+#  modification, are permitted provided that the following conditions are met:
+#
+#  1. Redistributions of source code must retain the above copyright notice,
+#  this list of conditions and the following disclaimer.
+#
+#  2. Redistributions in binary form must reproduce the above copyright notice,
+#  this list of conditions and the following disclaimer in the documentation
+#  and/or other materials provided with the distribution.
+#
+#  3. Neither the name of the copyright holder nor the names of its contributors
+#  may be used to endorse or promote products derived from this software
+#  without specific prior written permission.
+#
+#  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+#  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+#  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+#  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+#  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+#  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+#  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+#  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+#  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+#  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+#  POSSIBILITY OF SUCH DAMAGE.
+#
+#  Author: Lisa Hsu
+#
+
+import math
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+from Ruby import create_topology
+from Ruby import send_evicts
+
+from Cluster import Cluster
+from Crossbar import Crossbar
+
+class CntrlBase:
+    _seqs = 0
+    @classmethod
+    def seqCount(cls):
+        # Use SeqCount not class since we need global count
+        CntrlBase._seqs += 1
+        return CntrlBase._seqs - 1
+
+    _cntrls = 0
+    @classmethod
+    def cntrlCount(cls):
+        # Use CntlCount not class since we need global count
+        CntrlBase._cntrls += 1
+        return CntrlBase._cntrls - 1
+
+    _version = 0
+    @classmethod
+    def versionCount(cls):
+        cls._version += 1 # Use count for this particular type
+        return cls._version - 1
+
+class L1DCache(RubyCache):
+    resourceStalls = False
+    def create(self, options):
+        self.size = MemorySize(options.l1d_size)
+        self.assoc = options.l1d_assoc
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+class L1ICache(RubyCache):
+    resourceStalls = False
+    def create(self, options):
+        self.size = MemorySize(options.l1i_size)
+        self.assoc = options.l1i_assoc
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+class L2Cache(RubyCache):
+    resourceStalls = False
+    def create(self, options):
+        self.size = MemorySize(options.l2_size)
+        self.assoc = options.l2_assoc
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+class CPCntrl(CorePair_Controller, CntrlBase):
+
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+
+        self.L1Icache = L1ICache()
+        self.L1Icache.create(options)
+        self.L1D0cache = L1DCache()
+        self.L1D0cache.create(options)
+        self.L1D1cache = L1DCache()
+        self.L1D1cache.create(options)
+        self.L2cache = L2Cache()
+        self.L2cache.create(options)
+
+        self.sequencer = RubySequencer()
+        self.sequencer.icache_hit_latency = 2
+        self.sequencer.dcache_hit_latency = 2
+        self.sequencer.version = self.seqCount()
+        self.sequencer.icache = self.L1Icache
+        self.sequencer.dcache = self.L1D0cache
+        self.sequencer.ruby_system = ruby_system
+        self.sequencer.coreid = 0
+        self.sequencer.is_cpu_sequencer = True
+
+        self.sequencer1 = RubySequencer()
+        self.sequencer1.version = self.seqCount()
+        self.sequencer1.icache = self.L1Icache
+        self.sequencer1.dcache = self.L1D1cache
+        self.sequencer1.icache_hit_latency = 2
+        self.sequencer1.dcache_hit_latency = 2
+        self.sequencer1.ruby_system = ruby_system
+        self.sequencer1.coreid = 1
+        self.sequencer1.is_cpu_sequencer = True
+
+        self.issue_latency = options.cpu_to_dir_latency
+        self.send_evictions = send_evicts(options)
+
+        self.ruby_system = ruby_system
+
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+class L3Cache(RubyCache):
+    assoc = 8
+    dataArrayBanks = 256
+    tagArrayBanks = 256
+
+    def create(self, options, ruby_system, system):
+        self.size = MemorySize(options.l3_size)
+        self.size.value /= options.num_dirs
+        self.dataArrayBanks /= options.num_dirs
+        self.tagArrayBanks /= options.num_dirs
+        self.dataArrayBanks /= options.num_dirs
+        self.tagArrayBanks /= options.num_dirs
+        self.dataAccessLatency = options.l3_data_latency
+        self.tagAccessLatency = options.l3_tag_latency
+        self.resourceStalls = options.no_resource_stalls
+        self.replacement_policy = PseudoLRUReplacementPolicy()
+
+class L3Cntrl(L3Cache_Controller, CntrlBase):
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+        self.L3cache = L3Cache()
+        self.L3cache.create(options, ruby_system, system)
+
+        self.l3_response_latency = max(self.L3cache.dataAccessLatency,
+                                       self.L3cache.tagAccessLatency)
+        self.ruby_system = ruby_system
+
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+    def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir,
+                           req_to_l3, probe_to_l3, resp_to_l3):
+        self.reqToDir = req_to_dir
+        self.respToDir = resp_to_dir
+        self.l3UnblockToDir = l3_unblock_to_dir
+        self.reqToL3 = req_to_l3
+        self.probeToL3 = probe_to_l3
+        self.respToL3 = resp_to_l3
+
+class DirMem(RubyDirectoryMemory, CntrlBase):
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+
+        phys_mem_size = AddrRange(options.mem_size).size()
+        mem_module_size = phys_mem_size / options.num_dirs
+        dir_size = MemorySize('0B')
+        dir_size.value = mem_module_size
+        self.size = dir_size
+
+class DirCntrl(Directory_Controller, CntrlBase):
+    def create(self, options, ruby_system, system):
+        self.version = self.versionCount()
+
+        self.response_latency = 30
+
+        self.directory = DirMem()
+        self.directory.create(options, ruby_system, system)
+
+        self.L3CacheMemory = L3Cache()
+        self.L3CacheMemory.create(options, ruby_system, system)
+
+        self.l3_hit_latency = max(self.L3CacheMemory.dataAccessLatency,
+                                  self.L3CacheMemory.tagAccessLatency)
+
+        self.number_of_TBEs = options.num_tbes
+
+        self.ruby_system = ruby_system
+
+        if options.recycle_latency:
+            self.recycle_latency = options.recycle_latency
+
+        self.CPUonly = True
+
+    def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir,
+                           req_to_l3, probe_to_l3, resp_to_l3):
+        self.reqToDir = req_to_dir
+        self.respToDir = resp_to_dir
+        self.l3UnblockToDir = l3_unblock_to_dir
+        self.reqToL3 = req_to_l3
+        self.probeToL3 = probe_to_l3
+        self.respToL3 = resp_to_l3
+
+def define_options(parser):
+    parser.add_option("--num-subcaches", type="int", default=4)
+    parser.add_option("--l3-data-latency", type="int", default=20)
+    parser.add_option("--l3-tag-latency", type="int", default=15)
+    parser.add_option("--cpu-to-dir-latency", type="int", default=15)
+    parser.add_option("--no-resource-stalls", action="store_false",
+                      default=True)
+    parser.add_option("--num-tbes", type="int", default=256)
+    parser.add_option("--l2-latency", type="int", default=50) # load to use
+
+def create_system(options, full_system, system, dma_devices, ruby_system):
+    if buildEnv['PROTOCOL'] != 'MOESI_AMD_Base':
+        panic("This script requires the MOESI_AMD_Base protocol.")
+
+    cpu_sequencers = []
+
+    #
+    # The ruby network creation expects the list of nodes in the system to
+    # be consistent with the NetDest list.  Therefore the l1 controller
+    # nodes must be listed before the directory nodes and directory nodes
+    # before dma nodes, etc.
+    #
+    l1_cntrl_nodes = []
+    l3_cntrl_nodes = []
+    dir_cntrl_nodes = []
+
+    control_count = 0
+
+    #
+    # Must create the individual controllers before the network to ensure
+    # the controller constructors are called before the network constructor
+    #
+
+    # This is the base crossbar that connects the L3s, Dirs, and cpu
+    # Cluster
+    mainCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s
+    for i in xrange(options.num_dirs):
+
+        dir_cntrl = DirCntrl(TCC_select_num_bits = 0)
+        dir_cntrl.create(options, ruby_system, system)
+
+        # Connect the Directory controller to the ruby network
+        dir_cntrl.requestFromCores = MessageBuffer(ordered = True)
+        dir_cntrl.requestFromCores.slave = ruby_system.network.master
+
+        dir_cntrl.responseFromCores = MessageBuffer()
+        dir_cntrl.responseFromCores.slave = ruby_system.network.master
+
+        dir_cntrl.unblockFromCores = MessageBuffer()
+        dir_cntrl.unblockFromCores.slave = ruby_system.network.master
+
+        dir_cntrl.probeToCore = MessageBuffer()
+        dir_cntrl.probeToCore.master = ruby_system.network.slave
+
+        dir_cntrl.responseToCore = MessageBuffer()
+        dir_cntrl.responseToCore.master = ruby_system.network.slave
+
+        dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
+        dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True)
+        dir_cntrl.responseFromMemory = MessageBuffer()
+
+        exec("system.dir_cntrl%d = dir_cntrl" % i)
+        dir_cntrl_nodes.append(dir_cntrl)
+
+        mainCluster.add(dir_cntrl)
+
+    # Technically this config can support an odd number of cpus, but the top
+    # level config files, such as the ruby_random_tester, will get confused if
+    # the number of cpus does not equal the number of sequencers.  Thus make
+    # sure that an even number of cpus is specified.
+    assert((options.num_cpus % 2) == 0)
+
+    # For an odd number of CPUs, still create the right number of controllers
+    cpuCluster = Cluster(extBW = 512, intBW = 512)  # 1 TB/s
+    for i in xrange((options.num_cpus + 1) / 2):
+
+        cp_cntrl = CPCntrl()
+        cp_cntrl.create(options, ruby_system, system)
+
+        exec("system.cp_cntrl%d = cp_cntrl" % i)
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1])
+
+        # Connect the CP controllers and the network
+        cp_cntrl.requestFromCore = MessageBuffer()
+        cp_cntrl.requestFromCore.master = ruby_system.network.slave
+
+        cp_cntrl.responseFromCore = MessageBuffer()
+        cp_cntrl.responseFromCore.master = ruby_system.network.slave
+
+        cp_cntrl.unblockFromCore = MessageBuffer()
+        cp_cntrl.unblockFromCore.master = ruby_system.network.slave
+
+        cp_cntrl.probeToCore = MessageBuffer()
+        cp_cntrl.probeToCore.slave = ruby_system.network.master
+
+        cp_cntrl.responseToCore = MessageBuffer()
+        cp_cntrl.responseToCore.slave = ruby_system.network.master
+
+        cp_cntrl.mandatoryQueue = MessageBuffer()
+        cp_cntrl.triggerQueue = MessageBuffer(ordered = True)
+
+        cpuCluster.add(cp_cntrl)
+
+    # Assuming no DMA devices
+    assert(len(dma_devices) == 0)
+
+    # Add cpu/gpu clusters to main cluster
+    mainCluster.add(cpuCluster)
+
+    ruby_system.network.number_of_virtual_networks = 10
+
+    return (cpu_sequencers, dir_cntrl_nodes, mainCluster)