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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-10-22 20:59:22 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-10-22 20:59:22 -0700 |
| commit | df3fd79d1fd4ce1b7621a834efe124a5b16affb2 (patch) | |
| tree | ac9ad71a703f4438c17ec2a5ca800891c6f0ea62 /configs/splash2/run.py | |
| parent | 2eae11be6499effbcf33e4f3ea747a7280adf86c (diff) | |
| download | gem5-df3fd79d1fd4ce1b7621a834efe124a5b16affb2.tar.xz | |
Configs: Stop setting the "mem" parameter in splash2 config files.
This parameter is no longer used, and trying to set it like these scripts were
gives a simobject two parents and causes the simulation to die.
Diffstat (limited to 'configs/splash2/run.py')
| -rw-r--r-- | configs/splash2/run.py | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/configs/splash2/run.py b/configs/splash2/run.py index 24faade17..8d42b3ab8 100644 --- a/configs/splash2/run.py +++ b/configs/splash2/run.py @@ -217,7 +217,6 @@ system.l2.mem_side = system.membus.port for cpu in cpus: cpu.addPrivateSplitL1Caches(L1(size = options.l1size, assoc = 1), L1(size = options.l1size, assoc = 4)) - cpu.mem = cpu.dcache # connect cpu level-1 caches to shared level-2 cache cpu.connectMemPorts(system.toL2bus) |