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authorAndreas Hansson <andreas.hansson@arm.com>2012-02-14 14:15:30 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2012-02-14 14:15:30 -0500
commit6cf9f182f678e4ddf2a2b98a5093a7418353217c (patch)
tree9de2665814818b7ce04cf7b2c85cc907b71a3581 /configs/splash2/run.py
parentac91f90145f824b202d79a9e275fc5cee1071159 (diff)
downloadgem5-6cf9f182f678e4ddf2a2b98a5093a7418353217c.tar.xz
MEM: Fix residual bus ports and make them master/slave
This patch cleans up a number of remaining uses of bus.port which is now split into bus.master and bus.slave. The only non-trivial change is the memtest where the level building now has to be aware of the role of the ports used in the previous level.
Diffstat (limited to 'configs/splash2/run.py')
-rw-r--r--configs/splash2/run.py8
1 files changed, 4 insertions, 4 deletions
diff --git a/configs/splash2/run.py b/configs/splash2/run.py
index 23e986b09..2681a222d 100644
--- a/configs/splash2/run.py
+++ b/configs/splash2/run.py
@@ -207,10 +207,10 @@ system.l2 = L2(size = options.l2size, assoc = 8)
# Connect the L2 cache and memory together
# ----------------------
-system.physmem.port = system.membus.port
-system.l2.cpu_side = system.toL2bus.port
-system.l2.mem_side = system.membus.port
-system.system_port = system.membus.port
+system.physmem.port = system.membus.master
+system.l2.cpu_side = system.toL2bus.master
+system.l2.mem_side = system.membus.slave
+system.system_port = system.membus.slave
# ----------------------
# Connect the L2 cache and clusters together