MEM: Fix residual bus ports and make them master/slave

This patch cleans up a number of remaining uses of bus.port which
is now split into bus.master and bus.slave. The only non-trivial change
is the memtest where the level building now has to be aware of the role
of the ports used in the previous level.

1 files changed, 4 insertions, 4 deletions

diff --git a/configs/splash2/run.py b/configs/splash2/run.py
index 23e986b09..2681a222d 100644
--- a/configs/splash2/run.py
+++ b/configs/splash2/run.py
@@ -207,10 +207,10 @@ system.l2 = L2(size = options.l2size, assoc = 8)
 # Connect the L2 cache and memory together
 # ----------------------
 
-system.physmem.port = system.membus.port
-system.l2.cpu_side = system.toL2bus.port
-system.l2.mem_side = system.membus.port
-system.system_port = system.membus.port
+system.physmem.port = system.membus.master
+system.l2.cpu_side = system.toL2bus.master
+system.l2.mem_side = system.membus.slave
+system.system_port = system.membus.slave
 
 # ----------------------
 # Connect the L2 cache and clusters together