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| author | Gabe Black <gblack@eecs.umich.edu> | 2011-02-03 20:23:00 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-02-03 20:23:00 -0800 |
| commit | 00f24ae92c7b9aa73e12fd8160b5756e80126db2 (patch) | |
| tree | 1d149846db0efdc77c635891c6c1433d3af1817d /configs/splash2 | |
| parent | 869a046e413d7cbfdda4e33eed8191004017a83f (diff) | |
| download | gem5-00f24ae92c7b9aa73e12fd8160b5756e80126db2.tar.xz | |
Config: Keep track of uncached and cached ports separately.
This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.
Diffstat (limited to 'configs/splash2')
| -rw-r--r-- | configs/splash2/run.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/configs/splash2/run.py b/configs/splash2/run.py index 8d42b3ab8..200eb191d 100644 --- a/configs/splash2/run.py +++ b/configs/splash2/run.py @@ -218,7 +218,7 @@ for cpu in cpus: cpu.addPrivateSplitL1Caches(L1(size = options.l1size, assoc = 1), L1(size = options.l1size, assoc = 4)) # connect cpu level-1 caches to shared level-2 cache - cpu.connectMemPorts(system.toL2bus) + cpu.connectAllPorts(system.toL2bus, system.membus) # ---------------------- |