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| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:32 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:32 -0400 |
| commit | 1f6d5f8f849f50a3646f586b1274708537124ef3 (patch) | |
| tree | 03c98c46d500fbd9ac8135baea399813ea3d5644 /configs/splash2 | |
| parent | 1884bcc03ba2b6e734b4bd379d8542596e6d5c84 (diff) | |
| download | gem5-1f6d5f8f849f50a3646f586b1274708537124ef3.tar.xz | |
mem: Rename Bus to XBar to better reflect its behaviour
This patch changes the name of the Bus classes to XBar to better
reflect the actual timing behaviour. The actual instances in the
config scripts are not renamed, and remain as e.g. iobus or membus.
As part of this renaming, the code has also been clean up slightly,
making use of range-based for loops and tidying up some comments. The
only changes outside the bus/crossbar code is due to the delay
variables in the packet.
--HG--
rename : src/mem/Bus.py => src/mem/XBar.py
rename : src/mem/coherent_bus.cc => src/mem/coherent_xbar.cc
rename : src/mem/coherent_bus.hh => src/mem/coherent_xbar.hh
rename : src/mem/noncoherent_bus.cc => src/mem/noncoherent_xbar.cc
rename : src/mem/noncoherent_bus.hh => src/mem/noncoherent_xbar.hh
rename : src/mem/bus.cc => src/mem/xbar.cc
rename : src/mem/bus.hh => src/mem/xbar.hh
Diffstat (limited to 'configs/splash2')
| -rw-r--r-- | configs/splash2/cluster.py | 10 | ||||
| -rw-r--r-- | configs/splash2/run.py | 4 |
2 files changed, 7 insertions, 7 deletions
diff --git a/configs/splash2/cluster.py b/configs/splash2/cluster.py index 1ae9a6dd5..b17c8877e 100644 --- a/configs/splash2/cluster.py +++ b/configs/splash2/cluster.py @@ -171,7 +171,7 @@ if options.timing: for j in xrange(options.numclusters): clusters[j].id = j for cluster in clusters: - cluster.clusterbus = CoherentBus(clock=busFrequency) + cluster.clusterbus = CoherentXBar(clock=busFrequency) all_l1buses += [cluster.clusterbus] cluster.cpus = [TimingSimpleCPU(cpu_id = i + cluster.id, clock=options.frequency) @@ -184,7 +184,7 @@ elif options.detailed: for j in xrange(options.numclusters): clusters[j].id = j for cluster in clusters: - cluster.clusterbus = CoherentBus(clock=busFrequency) + cluster.clusterbus = CoherentXBar(clock=busFrequency) all_l1buses += [cluster.clusterbus] cluster.cpus = [DerivO3CPU(cpu_id = i + cluster.id, clock=options.frequency) @@ -197,7 +197,7 @@ else: for j in xrange(options.numclusters): clusters[j].id = j for cluster in clusters: - cluster.clusterbus = CoherentBus(clock=busFrequency) + cluster.clusterbus = CoherentXBar(clock=busFrequency) all_l1buses += [cluster.clusterbus] cluster.cpus = [AtomicSimpleCPU(cpu_id = i + cluster.id, clock=options.frequency) @@ -211,10 +211,10 @@ else: # ---------------------- system = System(cpu = all_cpus, l1_ = all_l1s, l1bus_ = all_l1buses, physmem = SimpleMemory(), - membus = CoherentBus(clock = busFrequency)) + membus = CoherentXBar(clock = busFrequency)) system.clock = '1GHz' -system.toL2bus = CoherentBus(clock = busFrequency) +system.toL2bus = CoherentXBar(clock = busFrequency) system.l2 = L2(size = options.l2size, assoc = 8) # ---------------------- diff --git a/configs/splash2/run.py b/configs/splash2/run.py index 10c9a7f61..d542a9437 100644 --- a/configs/splash2/run.py +++ b/configs/splash2/run.py @@ -196,10 +196,10 @@ else: # Create a system, and add system wide objects # ---------------------- system = System(cpu = cpus, physmem = SimpleMemory(), - membus = CoherentBus(clock = busFrequency)) + membus = CoherentXBar(clock = busFrequency)) system.clock = '1GHz' -system.toL2bus = CoherentBus(clock = busFrequency) +system.toL2bus = CoherentXBar(clock = busFrequency) system.l2 = L2(size = options.l2size, assoc = 8) # ---------------------- |