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| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 04:00:47 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 04:00:47 -0500 |
| commit | 36dc93a5fa09765b9d2bac402bb557d228effcad (patch) | |
| tree | 3a0899247304a0800653f73f515617027ee8dba0 /configs/splash2 | |
| parent | d35dd71ab4ac44a79ac22dca82277a43cd59f3c6 (diff) | |
| download | gem5-36dc93a5fa09765b9d2bac402bb557d228effcad.tar.xz | |
mem: Move crossbar default latencies to subclasses
This patch introduces a few subclasses to the CoherentXBar and
NoncoherentXBar to distinguish the different uses in the system. We
use the crossbar in a wide range of places: interfacing cores to the
L2, as a system interconnect, connecting I/O and peripherals,
etc. Needless to say, these crossbars have very different performance,
and the clock frequency alone is not enough to distinguish these
scenarios.
Instead of trying to capture every possible case, this patch
introduces dedicated subclasses for the three primary use-cases:
L2XBar, SystemXBar and IOXbar. More can be added if needed, and the
defaults can be overridden.
Diffstat (limited to 'configs/splash2')
| -rw-r--r-- | configs/splash2/cluster.py | 10 | ||||
| -rw-r--r-- | configs/splash2/run.py | 4 |
2 files changed, 7 insertions, 7 deletions
diff --git a/configs/splash2/cluster.py b/configs/splash2/cluster.py index b17c8877e..9fafcb70c 100644 --- a/configs/splash2/cluster.py +++ b/configs/splash2/cluster.py @@ -171,7 +171,7 @@ if options.timing: for j in xrange(options.numclusters): clusters[j].id = j for cluster in clusters: - cluster.clusterbus = CoherentXBar(clock=busFrequency) + cluster.clusterbus = L2XBar(clock=busFrequency) all_l1buses += [cluster.clusterbus] cluster.cpus = [TimingSimpleCPU(cpu_id = i + cluster.id, clock=options.frequency) @@ -184,7 +184,7 @@ elif options.detailed: for j in xrange(options.numclusters): clusters[j].id = j for cluster in clusters: - cluster.clusterbus = CoherentXBar(clock=busFrequency) + cluster.clusterbus = L2XBar(clock=busFrequency) all_l1buses += [cluster.clusterbus] cluster.cpus = [DerivO3CPU(cpu_id = i + cluster.id, clock=options.frequency) @@ -197,7 +197,7 @@ else: for j in xrange(options.numclusters): clusters[j].id = j for cluster in clusters: - cluster.clusterbus = CoherentXBar(clock=busFrequency) + cluster.clusterbus = L2XBar(clock=busFrequency) all_l1buses += [cluster.clusterbus] cluster.cpus = [AtomicSimpleCPU(cpu_id = i + cluster.id, clock=options.frequency) @@ -211,10 +211,10 @@ else: # ---------------------- system = System(cpu = all_cpus, l1_ = all_l1s, l1bus_ = all_l1buses, physmem = SimpleMemory(), - membus = CoherentXBar(clock = busFrequency)) + membus = SystemXBar(clock = busFrequency)) system.clock = '1GHz' -system.toL2bus = CoherentXBar(clock = busFrequency) +system.toL2bus = L2XBar(clock = busFrequency) system.l2 = L2(size = options.l2size, assoc = 8) # ---------------------- diff --git a/configs/splash2/run.py b/configs/splash2/run.py index d542a9437..14e5f47d4 100644 --- a/configs/splash2/run.py +++ b/configs/splash2/run.py @@ -196,10 +196,10 @@ else: # Create a system, and add system wide objects # ---------------------- system = System(cpu = cpus, physmem = SimpleMemory(), - membus = CoherentXBar(clock = busFrequency)) + membus = SystemXBar(clock = busFrequency)) system.clock = '1GHz' -system.toL2bus = CoherentXBar(clock = busFrequency) +system.toL2bus = L2XBar(clock = busFrequency) system.l2 = L2(size = options.l2size, assoc = 8) # ---------------------- |