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authorAndreas Hansson <andreas.hansson@arm.com>2012-04-06 13:46:31 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-04-06 13:46:31 -0400
commitb00949d88bb3185dfa2e27799de7f90e5a449be8 (patch)
tree74789b938463bcf38d5ffd5e6be5ef7a02d84a58 /configs/splash2
parentdbe1608fd58d818f59a0adf5f3fb562f61242f99 (diff)
downloadgem5-b00949d88bb3185dfa2e27799de7f90e5a449be8.tar.xz
MEM: Enable multiple distributed generalized memories
This patch removes the assumption on having on single instance of PhysicalMemory, and enables a distributed memory where the individual memories in the system are each responsible for a single contiguous address range. All memories inherit from an AbstractMemory that encompasses the basic behaviuor of a random access memory, and provides untimed access methods. What was previously called PhysicalMemory is now SimpleMemory, and a subclass of AbstractMemory. All future types of memory controllers should inherit from AbstractMemory. To enable e.g. the atomic CPU and RubyPort to access the now distributed memory, the system has a wrapper class, called PhysicalMemory that is aware of all the memories in the system and their associated address ranges. This class thus acts as an infinitely-fast bus and performs address decoding for these "shortcut" accesses. Each memory can specify that it should not be part of the global address map (used e.g. by the functional memories by some testers). Moreover, each memory can be configured to be reported to the OS configuration table, useful for populating ATAG structures, and any potential ACPI tables. Checkpointing support currently assumes that all memories have the same size and organisation when creating and resuming from the checkpoint. A future patch will enable a more flexible re-organisation. --HG-- rename : src/mem/PhysicalMemory.py => src/mem/AbstractMemory.py rename : src/mem/PhysicalMemory.py => src/mem/SimpleMemory.py rename : src/mem/physical.cc => src/mem/abstract_mem.cc rename : src/mem/physical.hh => src/mem/abstract_mem.hh rename : src/mem/physical.cc => src/mem/simple_mem.cc rename : src/mem/physical.hh => src/mem/simple_mem.hh
Diffstat (limited to 'configs/splash2')
-rw-r--r--configs/splash2/cluster.py4
-rw-r--r--configs/splash2/run.py2
2 files changed, 3 insertions, 3 deletions
diff --git a/configs/splash2/cluster.py b/configs/splash2/cluster.py
index a6244a9ef..dd8ab784a 100644
--- a/configs/splash2/cluster.py
+++ b/configs/splash2/cluster.py
@@ -211,8 +211,8 @@ else:
# ----------------------
# Create a system, and add system wide objects
# ----------------------
-system = System(cpu = all_cpus, l1_ = all_l1s, l1bus_ = all_l1buses, physmem = PhysicalMemory(),
- membus = Bus(clock = busFrequency))
+system = System(cpu = all_cpus, l1_ = all_l1s, l1bus_ = all_l1buses,
+ physmem = SimpleMemory(), membus = Bus(clock = busFrequency))
system.toL2bus = Bus(clock = busFrequency)
system.l2 = L2(size = options.l2size, assoc = 8)
diff --git a/configs/splash2/run.py b/configs/splash2/run.py
index 2681a222d..40dafceff 100644
--- a/configs/splash2/run.py
+++ b/configs/splash2/run.py
@@ -197,7 +197,7 @@ else:
# ----------------------
# Create a system, and add system wide objects
# ----------------------
-system = System(cpu = cpus, physmem = PhysicalMemory(),
+system = System(cpu = cpus, physmem = SimpleMemory(),
membus = Bus(clock = busFrequency))
system.toL2bus = Bus(clock = busFrequency)