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authorTushar Krishna <tushar@ece.gatech.edu>2016-10-06 14:35:18 -0400
committerTushar Krishna <tushar@ece.gatech.edu>2016-10-06 14:35:18 -0400
commit003c08fa90f8b3eb7fbbbc96e0caa5f46bf58196 (patch)
tree13b408554ffbebd11ae2322e8a070a0c4d5b9c56 /configs/topologies/MeshDirCorners_XY.py
parentb9e23a6d741cdcdf0ffb7364c6aae36a487335ef (diff)
downloadgem5-003c08fa90f8b3eb7fbbbc96e0caa5f46bf58196.tar.xz
config: make internal links in network topology unidirectional.
This patch makes the internal links within the network topology unidirectional, thus allowing any deadlock-free routing algorithms to be specified from the topology itself using weights. This patch also renames Mesh.py and MeshDirCorners.py to Mesh_XY.py and MeshDirCorners_XY.py (Mesh with XY routing). It also adds a Mesh_westfirst.py and CrossbarGarnet.py topologies.
Diffstat (limited to 'configs/topologies/MeshDirCorners_XY.py')
-rw-r--r--configs/topologies/MeshDirCorners_XY.py164
1 files changed, 164 insertions, 0 deletions
diff --git a/configs/topologies/MeshDirCorners_XY.py b/configs/topologies/MeshDirCorners_XY.py
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+++ b/configs/topologies/MeshDirCorners_XY.py
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+# Copyright (c) 2010 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Brad Beckmann
+
+from m5.params import *
+from m5.objects import *
+
+from BaseTopology import SimpleTopology
+
+# Creates a Mesh topology with 4 directories, one at each corner.
+# One L1 (and L2, depending on the protocol) are connected to each router.
+# XY routing is enforced (using link weights) to guarantee deadlock freedom.
+
+class MeshDirCorners_XY(SimpleTopology):
+ description='MeshDirCorners_XY'
+
+ def __init__(self, controllers):
+ self.nodes = controllers
+
+ def makeTopology(self, options, network, IntLink, ExtLink, Router):
+ nodes = self.nodes
+
+ num_routers = options.num_cpus
+ num_rows = options.mesh_rows
+
+ # First determine which nodes are cache cntrls vs. dirs vs. dma
+ cache_nodes = []
+ dir_nodes = []
+ dma_nodes = []
+ for node in nodes:
+ if node.type == 'L1Cache_Controller' or \
+ node.type == 'L2Cache_Controller':
+ cache_nodes.append(node)
+ elif node.type == 'Directory_Controller':
+ dir_nodes.append(node)
+ elif node.type == 'DMA_Controller':
+ dma_nodes.append(node)
+
+ # Obviously the number or rows must be <= the number of routers
+ # and evenly divisible. Also the number of caches must be a
+ # multiple of the number of routers and the number of directories
+ # must be four.
+ assert(num_rows <= num_routers)
+ num_columns = int(num_routers / num_rows)
+ assert(num_columns * num_rows == num_routers)
+ caches_per_router, remainder = divmod(len(cache_nodes), num_routers)
+ assert(remainder == 0)
+ assert(len(dir_nodes) == 4)
+
+ # Create the routers in the mesh
+ routers = [Router(router_id=i) for i in range(num_routers)]
+ network.routers = routers
+
+ # link counter to set unique link ids
+ link_count = 0
+
+ # Connect each cache controller to the appropriate router
+ ext_links = []
+ for (i, n) in enumerate(cache_nodes):
+ cntrl_level, router_id = divmod(i, num_routers)
+ assert(cntrl_level < caches_per_router)
+ ext_links.append(ExtLink(link_id=link_count, ext_node=n,
+ int_node=routers[router_id]))
+ link_count += 1
+
+ # Connect the dir nodes to the corners.
+ ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[0],
+ int_node=routers[0]))
+ link_count += 1
+ ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[1],
+ int_node=routers[num_columns - 1]))
+ link_count += 1
+ ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[2],
+ int_node=routers[num_routers - num_columns]))
+ link_count += 1
+ ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[3],
+ int_node=routers[num_routers - 1]))
+ link_count += 1
+
+ # Connect the dma nodes to router 0. These should only be DMA nodes.
+ for (i, node) in enumerate(dma_nodes):
+ assert(node.type == 'DMA_Controller')
+ ext_links.append(ExtLink(link_id=link_count, ext_node=node,
+ int_node=routers[0]))
+
+ network.ext_links = ext_links
+
+ # Create the mesh links.
+ int_links = []
+
+ # East output to West input links (weight = 1)
+ for row in xrange(num_rows):
+ for col in xrange(num_columns):
+ if (col + 1 < num_columns):
+ east_out = col + (row * num_columns)
+ west_in = (col + 1) + (row * num_columns)
+ int_links.append(IntLink(link_id=link_count,
+ src_node=routers[east_out],
+ dst_node=routers[west_in],
+ weight=1))
+ link_count += 1
+
+ # West output to East input links (weight = 1)
+ for row in xrange(num_rows):
+ for col in xrange(num_columns):
+ if (col + 1 < num_columns):
+ east_in = col + (row * num_columns)
+ west_out = (col + 1) + (row * num_columns)
+ int_links.append(IntLink(link_id=link_count,
+ src_node=routers[west_out],
+ dst_node=routers[east_in],
+ weight=1))
+ link_count += 1
+
+ # North output to South input links (weight = 2)
+ for col in xrange(num_columns):
+ for row in xrange(num_rows):
+ if (row + 1 < num_rows):
+ north_out = col + (row * num_columns)
+ south_in = col + ((row + 1) * num_columns)
+ int_links.append(IntLink(link_id=link_count,
+ src_node=routers[north_out],
+ dst_node=routers[south_in],
+ weight=2))
+ link_count += 1
+
+ # South output to North input links (weight = 2)
+ for col in xrange(num_columns):
+ for row in xrange(num_rows):
+ if (row + 1 < num_rows):
+ north_in = col + (row * num_columns)
+ south_out = col + ((row + 1) * num_columns)
+ int_links.append(IntLink(link_id=link_count,
+ src_node=routers[south_out],
+ dst_node=routers[north_in],
+ weight=2))
+ link_count += 1
+
+
+ network.int_links = int_links