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authorNikos Nikoleris <nikos.nikoleris@arm.com>2019-09-12 16:10:26 +0100
committerNikos Nikoleris <nikos.nikoleris@arm.com>2019-10-29 09:48:10 +0000
commit39220ef3681deb8c224cdcf28efdaa74bfa2facd (patch)
tree58552932697f996b2a30ab336a862dd03b9a4619 /configs
parent12cf816745fa9fe2718e54d19b33f303b15b90aa (diff)
downloadgem5-39220ef3681deb8c224cdcf28efdaa74bfa2facd.tar.xz
mem: Fix DRAM controller to operate on its own address space
Typically, a memory controller is assigned an address range of the form [start, end). This address range might be interleaved and therefore only a non-continuous subset of the addresses in the address range is handed by this controller. Prior to this patch, the DRAM controller was unaware of the interleaving and as a result the address range could affect the mapping of addresses to DRAM ranks, rows and columns. This patch changes the DRAM controller, to transform the input address to a continuous range of the form [0, size). As a result the DRAM controller always operates on a dense and continuous address range regardlesss of the system configuration. Change-Id: I7d273a630928421d1854658c9bb0ab34e9360851 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19328 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'configs')
-rw-r--r--configs/common/MemConfig.py4
1 files changed, 0 insertions, 4 deletions
diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index 7f737761e..0b5011c36 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -66,10 +66,6 @@ def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size):
# Only do this for DRAMs
if issubclass(cls, m5.objects.DRAMCtrl):
- # Inform each controller how many channels to account
- # for
- ctrl.channels = nbr_mem_ctrls
-
# If the channel bits are appearing after the column
# bits, we need to add the appropriate number of bits
# for the row buffer size