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authorAndreas Hansson <andreas.hansson@arm.com>2015-09-25 06:45:50 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2015-09-25 06:45:50 -0400
commit40fcb59c5440054f43675fd60ad8244c851f5050 (patch)
tree535ffbc730afb73bd19c7ece1befa09bb50434f3 /configs
parent4647e4e9612c040f84f0e6de6a8d7c8699f89aa2 (diff)
downloadgem5-40fcb59c5440054f43675fd60ad8244c851f5050.tar.xz
util: Fix minor issues in DRAM sweep scripts
This patch fixes a few issues in the sweep scripts, bringing them up-to-date with the latest memory configs and options.
Diffstat (limited to 'configs')
-rw-r--r--configs/dram/sweep.py11
1 files changed, 6 insertions, 5 deletions
diff --git a/configs/dram/sweep.py b/configs/dram/sweep.py
index 46c0b3d9a..eb4c9b41e 100644
--- a/configs/dram/sweep.py
+++ b/configs/dram/sweep.py
@@ -81,11 +81,11 @@ if args:
# at the moment we stay with the default open-adaptive page policy,
# and address mapping
-# start with the system itself, using a multi-layer 1.5 GHz
-# crossbar, delivering 64 bytes / 5 cycles (one header cycle)
-# which amounts to 19.2 GByte/s per layer and thus per port
-system = System(membus = IOXBar(width = 16))
-system.clk_domain = SrcClockDomain(clock = '1.5GHz',
+# start with the system itself, using a multi-layer 2.0 GHz
+# crossbar, delivering 64 bytes / 3 cycles (one header cycle)
+# which amounts to 42.7 GByte/s per layer and thus per port
+system = System(membus = IOXBar(width = 32))
+system.clk_domain = SrcClockDomain(clock = '2.0GHz',
voltage_domain =
VoltageDomain(voltage = '1V'))
@@ -100,6 +100,7 @@ mmap_using_noreserve = True
# generator
options.mem_channels = 1
options.external_memory_system = 0
+options.tlm_memory = 0
MemConfig.config_mem(options, system)
# the following assumes that we are using the native DRAM