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authorMarco Elver <Marco.Elver@ARM.com>2014-12-23 09:31:18 -0500
committerMarco Elver <Marco.Elver@ARM.com>2014-12-23 09:31:18 -0500
commit177682ead4e277cd25bcb92f7bdd9a37ada9c9cd (patch)
tree38581dd9ff175ef1313da30b6be3ab2df2c7a359 /configs
parentdd0f3943e20072021987780d6b15f531a4be2fca (diff)
downloadgem5-177682ead4e277cd25bcb92f7bdd9a37ada9c9cd.tar.xz
config: Add --memchecker option
This patch adds the --memchecker option, to denote that a MemChecker should be instantiated for the system. The exact usage of the MemChecker depends on the system configuration. For now CacheConfig.py makes use of the option, adding MemCheckerMonitor instances between CPUs and D-Caches. Note, however, that currently this only provides limited checking on a running system; other parts of the system, such as I/O devices are not monitored, and may cause warnings to be issued by the monitor.
Diffstat (limited to 'configs')
-rw-r--r--configs/common/CacheConfig.py25
-rw-r--r--configs/common/Options.py2
2 files changed, 27 insertions, 0 deletions
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index c7a724b34..f31b3d566 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -76,6 +76,9 @@ def config_cache(options, system):
system.l2.cpu_side = system.tol2bus.master
system.l2.mem_side = system.membus.slave
+ if options.memchecker:
+ system.memchecker = MemChecker()
+
for i in xrange(options.num_cpus):
if options.caches:
icache = icache_class(size=options.l1i_size,
@@ -83,6 +86,21 @@ def config_cache(options, system):
dcache = dcache_class(size=options.l1d_size,
assoc=options.l1d_assoc)
+ if options.memchecker:
+ dcache_mon = MemCheckerMonitor(warn_only=True)
+ dcache_real = dcache
+
+ # Do not pass the memchecker into the constructor of
+ # MemCheckerMonitor, as it would create a copy; we require
+ # exactly one MemChecker instance.
+ dcache_mon.memchecker = system.memchecker
+
+ # Connect monitor
+ dcache_mon.mem_side = dcache.cpu_side
+
+ # Let CPU connect to monitors
+ dcache = dcache_mon
+
# When connecting the caches, the clock is also inherited
# from the CPU in question
if buildEnv['TARGET_ISA'] == 'x86':
@@ -91,6 +109,13 @@ def config_cache(options, system):
PageTableWalkerCache())
else:
system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
+
+ if options.memchecker:
+ # The mem_side ports of the caches haven't been connected yet.
+ # Make sure connectAllPorts connects the right objects.
+ system.cpu[i].dcache = dcache_real
+ system.cpu[i].dcache_mon = dcache_mon
+
system.cpu[i].createInterruptController()
if options.l2cache:
system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
diff --git a/configs/common/Options.py b/configs/common/Options.py
index cb5ffad2e..f81e69a61 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -97,6 +97,8 @@ def addCommonOptions(parser):
parser.add_option("-l", "--lpae", action="store_true")
parser.add_option("-V", "--virtualisation", action="store_true")
+ parser.add_option("--memchecker", action="store_true")
+
# Cache Options
parser.add_option("--caches", action="store_true")
parser.add_option("--l2cache", action="store_true")