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authorAndreas Hansson <andreas.hansson@arm.com>2012-08-22 11:39:58 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-08-22 11:39:58 -0400
commita6074016e211276e47238d0d708288527ace0aef (patch)
tree6e0caa1639f3522e4379d3ab9827f195d9105f25 /configs
parente317d8b9ff611f16e116946054ac9a90cb453300 (diff)
downloadgem5-a6074016e211276e47238d0d708288527ace0aef.tar.xz
Bridge: Remove NACKs in the bridge and unify with packet queue
This patch removes the NACKing in the bridge, as the split request/response busses now ensure that protocol deadlocks do not occur, i.e. the message-dependency chain is broken by always allowing responses to make progress without being stalled by requests. The NACKs had limited support in the system with most components ignoring their use (with a suitable call to panic), and as the NACKs are no longer needed to avoid protocol deadlocks, the cleanest way is to simply remove them. The bridge is the starting point as this is the only place where the NACKs are created. A follow-up patch will remove the code that deals with NACKs in the endpoints, e.g. the X86 table walker and DMA port. Ultimately the type of packet can be complete removed (until someone sees a need for modelling more complex protocols, which can now be done in parts of the system since the port and interface is split). As a consequence of the NACK removal, the bridge now has to send a retry to a master if the request or response queue was full on the first attempt. This change also makes the bridge ports very similar to QueuedPorts, and a later patch will change the bridge to use these. A first step in this direction is taken by aligning the name of the member functions, as done by this patch. A bit of tidying up has also been done as part of the simplifications. Surprisingly, this patch has no impact on any of the regressions. Hence, there was never any NACKs issued. In a follow-up patch I would suggest changing the size of the bridge buffers set in FSConfig.py to also test the situation where the bridge fills up.
Diffstat (limited to 'configs')
-rw-r--r--configs/common/FSConfig.py12
-rw-r--r--configs/example/fs.py7
2 files changed, 9 insertions, 10 deletions
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 0e26242aa..0515fc53a 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -71,7 +71,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
self.membus = MemBus()
# By default the bridge responds to all addresses above the I/O
# base address (including the PCI config space)
- self.bridge = Bridge(delay='50ns', nack_delay='4ns',
+ self.bridge = Bridge(delay='50ns',
ranges = [AddrRange(IO_address_space_base, Addr.max)])
self.physmem = SimpleMemory(range = AddrRange(mdesc.mem()))
self.bridge.master = self.iobus.slave
@@ -174,7 +174,7 @@ def makeSparcSystem(mem_mode, mdesc = None):
self.readfile = mdesc.script()
self.iobus = NoncoherentBus()
self.membus = MemBus()
- self.bridge = Bridge(delay='50ns', nack_delay='4ns')
+ self.bridge = Bridge(delay='50ns')
self.t1000 = T1000()
self.t1000.attachOnChipIO(self.membus)
self.t1000.attachIO(self.iobus)
@@ -240,7 +240,7 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
self.iobus = NoncoherentBus()
self.membus = MemBus()
self.membus.badaddr_responder.warn_access = "warn"
- self.bridge = Bridge(delay='50ns', nack_delay='4ns')
+ self.bridge = Bridge(delay='50ns')
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
@@ -322,7 +322,7 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None):
self.readfile = mdesc.script()
self.iobus = NoncoherentBus()
self.membus = MemBus()
- self.bridge = Bridge(delay='50ns', nack_delay='4ns')
+ self.bridge = Bridge(delay='50ns')
self.physmem = SimpleMemory(range = AddrRange('1GB'))
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
@@ -368,7 +368,7 @@ def connectX86ClassicSystem(x86_sys, numCPUs):
# North Bridge
x86_sys.iobus = NoncoherentBus()
- x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns')
+ x86_sys.bridge = Bridge(delay='50ns')
x86_sys.bridge.master = x86_sys.iobus.slave
x86_sys.bridge.slave = x86_sys.membus.master
# Allow the bridge to pass through the IO APIC (two pages),
@@ -387,7 +387,7 @@ def connectX86ClassicSystem(x86_sys, numCPUs):
# Create a bridge from the IO bus to the memory bus to allow access to
# the local APIC (two pages)
- x86_sys.apicbridge = Bridge(delay='50ns', nack_delay='4ns')
+ x86_sys.apicbridge = Bridge(delay='50ns')
x86_sys.apicbridge.slave = x86_sys.iobus.master
x86_sys.apicbridge.master = x86_sys.membus.slave
x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
diff --git a/configs/example/fs.py b/configs/example/fs.py
index b0eb2f1ae..724e32813 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -126,8 +126,7 @@ if options.caches or options.l2cache:
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
else:
- test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
- ranges = [test_sys.physmem.range])
+ test_sys.iobridge = Bridge(delay='50ns', ranges = [test_sys.physmem.range])
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
@@ -162,8 +161,8 @@ if len(bm) == 2:
drive_sys.cpu.fastmem = True
if options.kernel is not None:
drive_sys.kernel = binary(options.kernel)
- drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
- ranges = [drive_sys.physmem.range])
+ drive_sys.iobridge = Bridge(delay='50ns',
+ ranges = [drive_sys.physmem.range])
drive_sys.iobridge.slave = drive_sys.iobus.master
drive_sys.iobridge.master = drive_sys.membus.slave