diff options
| author | Daniel R. Carvalho <odanrc@yahoo.com.br> | 2018-02-19 15:13:11 +0100 |
|---|---|---|
| committer | Daniel Carvalho <odanrc@yahoo.com.br> | 2018-03-22 14:50:23 +0000 |
| commit | d207e9ccee411877fdeac80bb68a27900560f50f (patch) | |
| tree | 120810cf72c52ed5df29436552e06f1fb11aa5ce /configs | |
| parent | 0473286ab1e9992a906eff380000bf90c82eeccb (diff) | |
| download | gem5-d207e9ccee411877fdeac80bb68a27900560f50f.tar.xz | |
mem-cache: Split array indexing and replacement policies.
Replacement policies (LRU, Random) are currently considered as array
indexing methods, but have completely different functionalities:
- Array indexers determine the possible locations for block allocation.
This information is used to generate replacement candidates when
conflicts happen.
- Replacement policies determine which of the replacement candidates
should be evicted to make room for new allocations.
For this reason, they were split into different classes. Advantages:
- Easier and more straightforward to implement other replacement
policies (RRIP, LFU, ARC, ...)
- Allow easier future implementation of cache organization schemes
As now we can't assure the use of sets, the previous way to create a
true LRU is not viable. Now a timestamp_bits parameter controls how
many bits are dedicated for the timestamp, and a true LRU can be
achieved through an infinite number of bits (although a few bits suffice
in practice).
Change-Id: I23750db121f1474d17831137e6ff618beb2b3eda
Reviewed-on: https://gem5-review.googlesource.com/8501
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/common/cores/arm/O3_ARM_v7a.py | 3 | ||||
| -rw-r--r-- | configs/common/cores/arm/ex5_LITTLE.py | 5 | ||||
| -rw-r--r-- | configs/common/cores/arm/ex5_big.py | 3 |
3 files changed, 6 insertions, 5 deletions
diff --git a/configs/common/cores/arm/O3_ARM_v7a.py b/configs/common/cores/arm/O3_ARM_v7a.py index fde4d3c60..b0ba1280f 100644 --- a/configs/common/cores/arm/O3_ARM_v7a.py +++ b/configs/common/cores/arm/O3_ARM_v7a.py @@ -201,4 +201,5 @@ class O3_ARM_v7aL2(Cache): clusivity = 'mostly_excl' # Simple stride prefetcher prefetcher = StridePrefetcher(degree=8, latency = 1) - tags = RandomRepl() + tags = BaseSetAssoc() + repl_policy = RandomRP() diff --git a/configs/common/cores/arm/ex5_LITTLE.py b/configs/common/cores/arm/ex5_LITTLE.py index a866b167b..1ae0f16df 100644 --- a/configs/common/cores/arm/ex5_LITTLE.py +++ b/configs/common/cores/arm/ex5_LITTLE.py @@ -145,6 +145,5 @@ class L2(Cache): clusivity = 'mostly_excl' # Simple stride prefetcher prefetcher = StridePrefetcher(degree=1, latency = 1) - tags = RandomRepl() - - + tags = BaseSetAssoc() + repl_policy = RandomRP() diff --git a/configs/common/cores/arm/ex5_big.py b/configs/common/cores/arm/ex5_big.py index f4ca04740..96323f435 100644 --- a/configs/common/cores/arm/ex5_big.py +++ b/configs/common/cores/arm/ex5_big.py @@ -197,4 +197,5 @@ class L2(Cache): clusivity = 'mostly_excl' # Simple stride prefetcher prefetcher = StridePrefetcher(degree=8, latency = 1) - tags = RandomRepl() + tags = BaseSetAssoc() + repl_policy = RandomRP() |