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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-01-07 07:38:53 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-01-07 07:38:53 -0600 |
| commit | 10c2e8ae9ae3f8f41f88fce7de4c2946d23a98fc (patch) | |
| tree | 0a135bfaa2a3c4d965286e63a21b83e4d38b0d00 /configs | |
| parent | ce941fd2ae2908dd0261132f35ab90e82c07b6b7 (diff) | |
| download | gem5-10c2e8ae9ae3f8f41f88fce7de4c2946d23a98fc.tar.xz | |
Ruby Cache: Add param for marking caches as instruction only
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/ruby/MOESI_hammer.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py index fb755ba55..4cc377ec8 100644 --- a/configs/ruby/MOESI_hammer.py +++ b/configs/ruby/MOESI_hammer.py @@ -88,7 +88,8 @@ def create_system(options, system, piobus, dma_devices, ruby_system): # l1i_cache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc, - start_index_bit = block_size_bits) + start_index_bit = block_size_bits, + is_icache = True) l1d_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, start_index_bit = block_size_bits) |