summaryrefslogtreecommitdiff
path: root/configs
diff options
context:
space:
mode:
authorChander Sudanthi <chander.sudanthi@arm.com>2011-12-01 00:15:22 -0800
committerChander Sudanthi <chander.sudanthi@arm.com>2011-12-01 00:15:22 -0800
commit61c14da751ae80e8c19e0b63ddd629c4152f1c72 (patch)
treea1c74b7afe115082c4ca5a5f1797d3de14772041 /configs
parentfa753c14549a768f0b8475e4e183acbdc394c248 (diff)
downloadgem5-61c14da751ae80e8c19e0b63ddd629c4152f1c72.tar.xz
O3: Remove hardcoded tgts_per_mshr in O3CPU.py.
There are two lines in O3CPU.py that set the dcache and icache tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr. This patch removes these hardcoded lines from O3CPU.py and sets the default L1 cache mshr targets to 20. --HG-- extra : rebase_source : 6f92d950e90496a3102967442814e97dc84db08b
Diffstat (limited to 'configs')
-rw-r--r--configs/common/Caches.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index ffcd63c49..0be8001d7 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -33,7 +33,7 @@ class L1Cache(BaseCache):
block_size = 64
latency = '1ns'
mshrs = 10
- tgts_per_mshr = 5
+ tgts_per_mshr = 20
is_top_level = True
class L2Cache(BaseCache):