ARM: Add support for Versatile Express extended memory map

Also clean up how we create boot loader memory a bit.

2 files changed, 13 insertions, 14 deletions

diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index fdc636a1f..85dfb10f4 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -252,6 +252,9 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
         self.realview = RealViewEB()
     elif machine_type == "VExpress_ELT":
         self.realview = VExpress_ELT()
+    elif machine_type == "VExpress_EMM":
+        self.realview = VExpress_EMM()
+        self.load_addr_mask = 0xffffffff
     else:
         print "Unknown Machine Type"
         sys.exit(1)
@@ -273,21 +276,17 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
     else:
         self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
         self.machine_type = machine_type
-        if convert.toMemorySize(mdesc.mem()) > convert.toMemorySize('256MB'):
-            print "The currently implemented ARM platforms only easily support 256MB of DRAM"
-            print "It might be possible to get some more by using 256MB@0x30000000, but this"
-            print "is untested and may require some heroics"
+        if convert.toMemorySize(mdesc.mem()) > self.realview.max_mem_size:
+            print "The currently selected ARM platforms doesn't support"
+            print " the amount of DRAM you've selected. Please try"
+            print " another platform"
 
         boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
                      'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
 
-        self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())),
-                                      zero = True)
-        self.nvmem = PhysicalMemory(range = AddrRange(Addr('2GB'),
-                                    size = '64MB'), zero = True)
-        self.nvmem.port = self.membus.master
-        self.boot_loader = binary('boot.arm')
-        self.boot_loader_mem = self.nvmem
+        self.physmem = PhysicalMemory(range = AddrRange(self.realview.mem_start_addr,
+                                                        size = mdesc.mem()))
+        self.realview.setupBootLoader(self.membus, self, binary)
         self.gic_cpu_addr = self.realview.gic.cpu_addr
         self.flags_addr = self.realview.realview_io.pio_addr + 0x30
 
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 41b4a75ae..7a0759e47 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -159,12 +159,12 @@ if bm[0]:
 else:
     mem_size = SysConfig().mem()
 if options.caches or options.l2cache:
-    test_sys.iocache = IOCache(addr_range=mem_size)
+    test_sys.iocache = IOCache(addr_range=test_sys.physmem.range)
     test_sys.iocache.cpu_side = test_sys.iobus.master
     test_sys.iocache.mem_side = test_sys.membus.slave
 else:
     test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
-                               ranges = [AddrRange(mem_size)])
+                               ranges = [test_sys.physmem.range])
     test_sys.iobridge.slave = test_sys.iobus.master
     test_sys.iobridge.master = test_sys.membus.slave
 
@@ -195,7 +195,7 @@ if len(bm) == 2:
     if options.kernel is not None:
         drive_sys.kernel = binary(options.kernel)
     drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
-                               ranges = [AddrRange(bm[1].mem())])
+                               ranges = [drive_sys.physmem.range])
     drive_sys.iobridge.slave = drive_sys.iobus.master
     drive_sys.iobridge.master = drive_sys.membus.slave