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authorBrad Beckmann <Brad.Beckmann@amd.com>2010-01-29 20:29:19 -0800
committerBrad Beckmann <Brad.Beckmann@amd.com>2010-01-29 20:29:19 -0800
commit2a0555470cfc66ab70544e97578c048822ec9282 (patch)
tree6f96f3fb5bf9f27b0c2c9032715907fa7939bc49 /configs
parent3b290a35aca3f6aba8226dde8387f38a9de39093 (diff)
downloadgem5-2a0555470cfc66ab70544e97578c048822ec9282.tar.xz
ruby: Converted MOESI_hammer dma cntrl to new config system
Diffstat (limited to 'configs')
-rw-r--r--configs/example/memtest-ruby.py11
1 files changed, 9 insertions, 2 deletions
diff --git a/configs/example/memtest-ruby.py b/configs/example/memtest-ruby.py
index c0569944e..abc22a93b 100644
--- a/configs/example/memtest-ruby.py
+++ b/configs/example/memtest-ruby.py
@@ -104,6 +104,7 @@ class L2Cache(RubyCache):
#
l1_cntrl_nodes = []
dir_cntrl_nodes = []
+dma_cntrl_nodes = []
#
# Must create the individual controllers before the network to ensure the
@@ -138,12 +139,15 @@ for (i, cpu) in enumerate(cpus):
directory = RubyDirectoryMemory(),
memBuffer = RubyMemoryControl())
+ dma_cntrl = DMA_Controller(version = i,
+ dma_sequencer = DMASequencer())
#
# As noted above: Two independent list are track to maintain the order of
# nodes/controllers assumed by the ruby network
#
l1_cntrl_nodes.append(l1_cntrl)
dir_cntrl_nodes.append(dir_cntrl)
+ dma_cntrl_nodes.append(dma_cntrl)
#
# Finally tie the memtester ports to the correct system ports
@@ -157,7 +161,8 @@ for (i, cpu) in enumerate(cpus):
# constructor.
#
network = SimpleNetwork(topology = makeCrossbar(l1_cntrl_nodes + \
- dir_cntrl_nodes))
+ dir_cntrl_nodes + \
+ dma_cntrl_nodes))
mem_size_mb = sum([int(dir_cntrl.directory.size_mb) \
for dir_cntrl in dir_cntrl_nodes])
@@ -166,7 +171,9 @@ system.ruby = RubySystem(clock = '1GHz',
network = network,
profiler = RubyProfiler(),
tracer = RubyTracer(),
- debug = RubyDebug(),
+ debug = RubyDebug(filter_string = 'qQin',
+ verbosity_string = 'high',
+ protocol_trace = True),
mem_size_mb = mem_size_mb)