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authorAndreas Hansson <andreas.hansson@arm.com>2012-02-14 14:15:30 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2012-02-14 14:15:30 -0500
commit6cf9f182f678e4ddf2a2b98a5093a7418353217c (patch)
tree9de2665814818b7ce04cf7b2c85cc907b71a3581 /configs
parentac91f90145f824b202d79a9e275fc5cee1071159 (diff)
downloadgem5-6cf9f182f678e4ddf2a2b98a5093a7418353217c.tar.xz
MEM: Fix residual bus ports and make them master/slave
This patch cleans up a number of remaining uses of bus.port which is now split into bus.master and bus.slave. The only non-trivial change is the memtest where the level building now has to be aware of the role of the ports used in the previous level.
Diffstat (limited to 'configs')
-rw-r--r--configs/example/memtest.py13
-rw-r--r--configs/splash2/cluster.py14
-rw-r--r--configs/splash2/run.py8
3 files changed, 22 insertions, 13 deletions
diff --git a/configs/example/memtest.py b/configs/example/memtest.py
index b2cedc8f5..5faee1bc7 100644
--- a/configs/example/memtest.py
+++ b/configs/example/memtest.py
@@ -147,11 +147,16 @@ def make_level(spec, prototypes, attach_obj, attach_port):
fanout = spec[0]
parent = attach_obj # use attach obj as config parent too
if len(spec) > 1 and (fanout > 1 or options.force_bus):
+ port = getattr(attach_obj, attach_port)
new_bus = Bus(clock="500MHz", width=16)
- new_bus.port = getattr(attach_obj, attach_port)
+ if (port.role == 'MASTER'):
+ new_bus.slave = port
+ attach_port = "master"
+ else:
+ new_bus.master = port
+ attach_port = "slave"
parent.cpu_side_bus = new_bus
attach_obj = new_bus
- attach_port = "port"
objs = [prototypes[0]() for i in xrange(fanout)]
if len(spec) > 1:
# we just built caches, more levels to go
@@ -178,6 +183,10 @@ if options.atomic:
else:
root.system.mem_mode = 'timing'
+# The system port is never used in the tester so merely connect it
+# to avoid problems
+root.system.system_port = root.system.physmem.port
+
# Not much point in this being higher than the L1 latency
m5.ticks.setGlobalFrequency('1ns')
diff --git a/configs/splash2/cluster.py b/configs/splash2/cluster.py
index 4a9446794..a6244a9ef 100644
--- a/configs/splash2/cluster.py
+++ b/configs/splash2/cluster.py
@@ -221,19 +221,19 @@ system.l2 = L2(size = options.l2size, assoc = 8)
# Connect the L2 cache and memory together
# ----------------------
-system.physmem.port = system.membus.port
-system.l2.cpu_side = system.toL2bus.port
-system.l2.mem_side = system.membus.port
+system.physmem.port = system.membus.master
+system.l2.cpu_side = system.toL2bus.slave
+system.l2.mem_side = system.membus.master
# ----------------------
# Connect the L2 cache and clusters together
# ----------------------
for cluster in clusters:
- cluster.l1.cpu_side = cluster.clusterbus.port
- cluster.l1.mem_side = system.toL2bus.port
+ cluster.l1.cpu_side = cluster.clusterbus.master
+ cluster.l1.mem_side = system.toL2bus.slave
for cpu in cluster.cpus:
- cpu.icache_port = cluster.clusterbus.port
- cpu.dcache_port = cluster.clusterbus.port
+ cpu.icache_port = cluster.clusterbus.slave
+ cpu.dcache_port = cluster.clusterbus.slave
# ----------------------
# Define the root
diff --git a/configs/splash2/run.py b/configs/splash2/run.py
index 23e986b09..2681a222d 100644
--- a/configs/splash2/run.py
+++ b/configs/splash2/run.py
@@ -207,10 +207,10 @@ system.l2 = L2(size = options.l2size, assoc = 8)
# Connect the L2 cache and memory together
# ----------------------
-system.physmem.port = system.membus.port
-system.l2.cpu_side = system.toL2bus.port
-system.l2.mem_side = system.membus.port
-system.system_port = system.membus.port
+system.physmem.port = system.membus.master
+system.l2.cpu_side = system.toL2bus.master
+system.l2.mem_side = system.membus.slave
+system.system_port = system.membus.slave
# ----------------------
# Connect the L2 cache and clusters together