testers: move testers to a new directory

This patch moves the testers to a new subdirectory under src/cpu and includes
the necessary fixes to work with latest m5 initialization patches.

--HG--
rename : configs/example/determ_test.py => configs/example/ruby_direct_test.py
rename : src/cpu/directedtest/DirectedGenerator.cc => src/cpu/testers/directedtest/DirectedGenerator.cc
rename : src/cpu/directedtest/DirectedGenerator.hh => src/cpu/testers/directedtest/DirectedGenerator.hh
rename : src/cpu/directedtest/InvalidateGenerator.cc => src/cpu/testers/directedtest/InvalidateGenerator.cc
rename : src/cpu/directedtest/InvalidateGenerator.hh => src/cpu/testers/directedtest/InvalidateGenerator.hh
rename : src/cpu/directedtest/RubyDirectedTester.cc => src/cpu/testers/directedtest/RubyDirectedTester.cc
rename : src/cpu/directedtest/RubyDirectedTester.hh => src/cpu/testers/directedtest/RubyDirectedTester.hh
rename : src/cpu/directedtest/RubyDirectedTester.py => src/cpu/testers/directedtest/RubyDirectedTester.py
rename : src/cpu/directedtest/SConscript => src/cpu/testers/directedtest/SConscript
rename : src/cpu/directedtest/SeriesRequestGenerator.cc => src/cpu/testers/directedtest/SeriesRequestGenerator.cc
rename : src/cpu/directedtest/SeriesRequestGenerator.hh => src/cpu/testers/directedtest/SeriesRequestGenerator.hh
rename : src/cpu/memtest/MemTest.py => src/cpu/testers/memtest/MemTest.py
rename : src/cpu/memtest/SConscript => src/cpu/testers/memtest/SConscript
rename : src/cpu/memtest/memtest.cc => src/cpu/testers/memtest/memtest.cc
rename : src/cpu/memtest/memtest.hh => src/cpu/testers/memtest/memtest.hh
rename : src/cpu/rubytest/Check.cc => src/cpu/testers/rubytest/Check.cc
rename : src/cpu/rubytest/Check.hh => src/cpu/testers/rubytest/Check.hh
rename : src/cpu/rubytest/CheckTable.cc => src/cpu/testers/rubytest/CheckTable.cc
rename : src/cpu/rubytest/CheckTable.hh => src/cpu/testers/rubytest/CheckTable.hh
rename : src/cpu/rubytest/RubyTester.cc => src/cpu/testers/rubytest/RubyTester.cc
rename : src/cpu/rubytest/RubyTester.hh => src/cpu/testers/rubytest/RubyTester.hh
rename : src/cpu/rubytest/RubyTester.py => src/cpu/testers/rubytest/RubyTester.py
rename : src/cpu/rubytest/SConscript => src/cpu/testers/rubytest/SConscript

4 files changed, 20 insertions, 17 deletions

diff --git a/configs/example/memtest-ruby.py b/configs/example/memtest-ruby.py
index d2e9c137e..e32e0c114 100644
--- a/configs/example/memtest-ruby.py
+++ b/configs/example/memtest-ruby.py
@@ -104,17 +104,21 @@ system = System(cpu = cpus,
                 funcmem = PhysicalMemory(),
                 physmem = PhysicalMemory())
 
-system.dmas = [ MemTest(atomic = False, \
-                        max_loads = options.maxloads, \
-                        issue_dmas = True, \
-                        percent_functional = 0, \
-                        percent_uncacheable = 0, \
-                        progress_interval = options.progress) \
-                for i in xrange(options.num_dmas) ]
+if options.num_dmas > 0:
+    dmas = [ MemTest(atomic = False, \
+                     max_loads = options.maxloads, \
+                     issue_dmas = True, \
+                     percent_functional = 0, \
+                     percent_uncacheable = 0, \
+                     progress_interval = options.progress) \
+             for i in xrange(options.num_dmas) ]
+    system.dma_devices = dmas
+else:
+    dmas = []
 
 system.ruby = Ruby.create_system(options, \
-                                 system.physmem, \
-                                 dma_devices = system.dmas)
+                                 system, \
+                                 dma_devices = dmas)
 
 #
 # The tester is most effective when randomization is turned on and
@@ -131,7 +135,7 @@ for (i, cpu) in enumerate(cpus):
     cpu.test = system.ruby.cpu_ruby_ports[i].port
     cpu.functional = system.funcmem.port
 
-for (i, dma) in enumerate(system.dmas):
+for (i, dma) in enumerate(dmas):
     #
     # Tie the dma memtester ports to the correct functional port
     # Note that the test port has already been connected to the dma_sequencer
diff --git a/configs/example/determ_test.py b/configs/example/ruby_direct_test.py
index 77712ffd9..e744c35bd 100644
--- a/configs/example/determ_test.py
+++ b/configs/example/ruby_direct_test.py
@@ -69,7 +69,7 @@ if args:
      sys.exit(1)
 
 #
-# Select the directed generator
+# Select the direct test generator
 #
 if options.test_type == "SeriesGetx":
     generator = SeriesRequestGenerator(num_cpus = options.num_cpus,
@@ -80,7 +80,7 @@ elif options.test_type == "SeriesGets":
 elif options.test_type == "Invalidate":
     generator = InvalidateGenerator(num_cpus = options.num_cpus)
 else:
-    print "Error: unknown directed generator"
+    print "Error: unknown direct test generator"
     sys.exit(1)
 
 #
@@ -95,7 +95,7 @@ system = System(physmem = PhysicalMemory())
 #
 system.tester = RubyDirectedTester(requests_to_complete = \
                                    options.requests,
-                                 generator = generator)
+                                   generator = generator)
 
 system.ruby = Ruby.create_system(options, system)
 
diff --git a/configs/example/rubytest.py b/configs/example/rubytest.py
index a4daf6b82..ddd6a53af 100644
--- a/configs/example/rubytest.py
+++ b/configs/example/rubytest.py
@@ -90,7 +90,7 @@ tester = RubyTester(checks_to_complete = options.checks,
 # actually used by the rubytester, but is included to support the
 # M5 memory size == Ruby memory size checks
 #
-system = System(physmem = PhysicalMemory())
+system = System(tester = tester, physmem = PhysicalMemory())
 
 system.ruby = Ruby.create_system(options, system)
 
diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index 3cd33f981..d1c1cc2b0 100644
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -186,10 +186,9 @@ def create_system(options, system, piobus, dma_devices):
 
         exec("system.dma_cntrl%d = dma_cntrl" % i)
         if dma_device.type == 'MemTest':
-            system.dma_cntrl.dma_sequencer.port = dma_device.test
+            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
         else:
-            system.dma_cntrl.dma_sequencer.port = dma_device.dma
-        dma_cntrl.dma_sequencer.port = dma_device.dma
+            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
         dma_cntrl_nodes.append(dma_cntrl)
 
         if options.recycle_latency: