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authorBrad Beckmann <Brad.Beckmann@amd.com>2010-01-29 20:29:22 -0800
committerBrad Beckmann <Brad.Beckmann@amd.com>2010-01-29 20:29:22 -0800
commitf88faa6c11bbb5c5f95fe32ccffca73c7c4758c8 (patch)
tree73f1ccfa1f56d86a8787f6e04a8c2cb116167e8c /configs
parentcfe41d0a1bc3b778995cd1b22f8d58037300143b (diff)
downloadgem5-f88faa6c11bbb5c5f95fe32ccffca73c7c4758c8.tar.xz
ruby: cleaned up ruby profilers
Cleaned up the ruby profilers by moving the memory controller profiling code out of the main profiler object and into a separate object similar to the current CacheProfiler. Both the CacheProfiler and MemCntrlProfiler are specific to a particular Ruby object, CacheMemory and MemoryControl respectively. Therefore, these profilers should not be SimObjects and created by the python configuration system, but instead private objects. This simplifies the creation of these profilers.
Diffstat (limited to 'configs')
-rw-r--r--configs/ruby/MOESI_hammer.py11
-rw-r--r--configs/ruby/Ruby.py15
2 files changed, 4 insertions, 22 deletions
diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index f35ab20c4..5273f597b 100644
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -74,14 +74,9 @@ def create_system(options, phys_mem, piobus, dma_devices):
#
# First create the Ruby objects associated with this cpu
#
- l1i_profiler = CacheProfiler(description = ("l1i_%s_profiler" % i))
- l1i_cache = L1Cache(cache_profiler = l1i_profiler)
-
- l1d_profiler = CacheProfiler(description = ("l1d_%s_profiler" % i))
- l1d_cache = L1Cache(cache_profiler = l1d_profiler)
-
- l2_profiler = CacheProfiler(description = ("l2_%s_profiler" % i))
- l2_cache = L2Cache(cache_profiler = l2_profiler)
+ l1i_cache = L1Cache()
+ l1d_cache = L1Cache()
+ l2_cache = L2Cache()
cpu_seq = RubySequencer(icache = l1i_cache,
dcache = l1d_cache,
diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index 37c43602d..abc9a8df5 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -57,20 +57,7 @@ def create_system(options, physmem, piobus = None, dma_devices = []):
mem_size_mb = sum([int(dir_cntrl.directory.size_mb) \
for dir_cntrl in dir_cntrls])
- #
- # determine the number of memory controllers and other memory controller
- # parameters for the profiler
- #
- mcCount = len(dir_cntrls)
- banksPerRank = dir_cntrls[0].memBuffer.banks_per_rank
- ranksPerDimm = dir_cntrls[0].memBuffer.ranks_per_dimm
- dimmsPerChannel = dir_cntrls[0].memBuffer.dimms_per_channel
-
- ruby_profiler = RubyProfiler(num_of_sequencers = len(cpu_sequencers),
- mem_cntrl_count = mcCount,
- banks_per_rank = banksPerRank,
- ranks_per_dimm = ranksPerDimm,
- dimms_per_channel = dimmsPerChannel)
+ ruby_profiler = RubyProfiler(num_of_sequencers = len(cpu_sequencers))
ruby = RubySystem(clock = options.clock,
network = network,