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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-11-29 17:34:20 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-11-29 17:34:20 -0500 |
| commit | 5bdf4400b223056d296ae27f4a7ee2f707a4d1bd (patch) | |
| tree | ff29e4424fe411d28b82ab653baa86a7f86ed18b /configs | |
| parent | f2daf210f1cac2dd0a102b9d796fb700d4be92d1 (diff) | |
| parent | 544f4b4d8156c1b7f779a2dd974cbff6a5b67c20 (diff) | |
| download | gem5-5bdf4400b223056d296ae27f4a7ee2f707a4d1bd.tar.xz | |
Merge zizzer:/bk/sparcfs
into zower.eecs.umich.edu:/eecshome/m5/newmemmid
src/arch/sparc/isa_traits.hh:
src/arch/sparc/miscregfile.hh:
hand merge
--HG--
extra : convert_revision : 34f50dc5e6e22096cb2c08b5888f2b0fcd418f3e
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/common/Simulation.py | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index 374ff3fc2..e037d0343 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -39,6 +39,9 @@ def setCPUClass(options): if options.timing: TmpClass = TimingSimpleCPU elif options.detailed: + if not options.caches: + print "O3 CPU must be used with caches" + sys.exit(1) TmpClass = DerivO3CPU else: TmpClass = AtomicSimpleCPU |