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authorNilay Vaish <nilay@cs.wisc.edu>2013-08-20 11:32:31 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2013-08-20 11:32:31 -0500
commitc4e7e18eeb72ede635ea75314406a19fa532fdd6 (patch)
treedb08ff711f1548f541679be9b7be94322da03972 /configs
parentc6062a3981e121d43ace2313766bdd4a1ce52d94 (diff)
downloadgem5-c4e7e18eeb72ede635ea75314406a19fa532fdd6.tar.xz
ruby: add option for number of transitions per cycle
The number of transitions per cycle that a controller can carry out is a proxy for the number of ports that a controller has. This value is currently 32 which is way too high. The patch introduces an option for the number of ports and uses this option in the protocol files to set the number of transitions. The default value is being set to 4. None of the se regressions change. Ruby stats for the fs regression change and are being updated.
Diffstat (limited to 'configs')
-rw-r--r--configs/ruby/MESI_CMP_directory.py4
-rw-r--r--configs/ruby/MI_example.py3
-rw-r--r--configs/ruby/MOESI_CMP_directory.py4
-rw-r--r--configs/ruby/MOESI_CMP_token.py4
-rw-r--r--configs/ruby/MOESI_hammer.py3
-rw-r--r--configs/ruby/Ruby.py5
6 files changed, 23 insertions, 0 deletions
diff --git a/configs/ruby/MESI_CMP_directory.py b/configs/ruby/MESI_CMP_directory.py
index 8cd74cde6..2dba25b1a 100644
--- a/configs/ruby/MESI_CMP_directory.py
+++ b/configs/ruby/MESI_CMP_directory.py
@@ -98,6 +98,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
options.cpu_type == "detailed"),
prefetcher = prefetcher,
ruby_system = ruby_system,
+ transitions_per_cycle=options.ports,
enable_prefetch = False)
cpu_seq = RubySequencer(version = i,
@@ -133,6 +134,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
l2_cntrl = L2Cache_Controller(version = i,
cntrl_id = cntrl_count,
L2cache = l2_cache,
+ transitions_per_cycle=options.ports,
ruby_system = ruby_system)
exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
@@ -172,6 +174,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
use_map =
options.use_map),
memBuffer = mem_cntrl,
+ transitions_per_cycle = options.ports,
ruby_system = ruby_system)
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
@@ -189,6 +192,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
dma_cntrl = DMA_Controller(version = i,
cntrl_id = cntrl_count,
dma_sequencer = dma_seq,
+ transitions_per_cycle = options.ports,
ruby_system = ruby_system)
exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py
index 44687e493..d7fa2d75d 100644
--- a/configs/ruby/MI_example.py
+++ b/configs/ruby/MI_example.py
@@ -84,6 +84,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
cacheMemory = cache,
send_evictions = (
options.cpu_type == "detailed"),
+ transitions_per_cycle = options.ports,
ruby_system = ruby_system)
cpu_seq = RubySequencer(version = i,
@@ -139,6 +140,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
map_levels = \
options.map_levels),
memBuffer = mem_cntrl,
+ transitions_per_cycle = options.ports,
ruby_system = ruby_system)
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
@@ -156,6 +158,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
dma_cntrl = DMA_Controller(version = i,
cntrl_id = cntrl_count,
dma_sequencer = dma_seq,
+ transitions_per_cycle = options.ports,
ruby_system = ruby_system)
exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
diff --git a/configs/ruby/MOESI_CMP_directory.py b/configs/ruby/MOESI_CMP_directory.py
index 33c62f7a3..30fa6479c 100644
--- a/configs/ruby/MOESI_CMP_directory.py
+++ b/configs/ruby/MOESI_CMP_directory.py
@@ -94,6 +94,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
l2_select_num_bits = l2_bits,
send_evictions = (
options.cpu_type == "detailed"),
+ transitions_per_cycle = options.ports,
ruby_system = ruby_system)
cpu_seq = RubySequencer(version = i,
@@ -128,6 +129,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
l2_cntrl = L2Cache_Controller(version = i,
cntrl_id = cntrl_count,
L2cache = l2_cache,
+ transitions_per_cycle = options.ports,
ruby_system = ruby_system)
exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
@@ -166,6 +168,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
size = dir_size,
use_map = options.use_map),
memBuffer = mem_cntrl,
+ transitions_per_cycle = options.ports,
ruby_system = ruby_system)
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
@@ -183,6 +186,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
dma_cntrl = DMA_Controller(version = i,
cntrl_id = cntrl_count,
dma_sequencer = dma_seq,
+ transitions_per_cycle = options.ports,
ruby_system = ruby_system)
exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
diff --git a/configs/ruby/MOESI_CMP_token.py b/configs/ruby/MOESI_CMP_token.py
index 43b9f97e8..c7ec908eb 100644
--- a/configs/ruby/MOESI_CMP_token.py
+++ b/configs/ruby/MOESI_CMP_token.py
@@ -114,6 +114,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
options.allow_atomic_migration,
send_evictions = (
options.cpu_type == "detailed"),
+ transitions_per_cycle = options.ports,
ruby_system = ruby_system)
cpu_seq = RubySequencer(version = i,
@@ -149,6 +150,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
cntrl_id = cntrl_count,
L2cache = l2_cache,
N_tokens = n_tokens,
+ transitions_per_cycle = options.ports,
ruby_system = ruby_system)
exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
@@ -188,6 +190,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
size = dir_size),
memBuffer = mem_cntrl,
l2_select_num_bits = l2_bits,
+ transitions_per_cycle = options.ports,
ruby_system = ruby_system)
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
@@ -205,6 +208,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
dma_cntrl = DMA_Controller(version = i,
cntrl_id = cntrl_count,
dma_sequencer = dma_seq,
+ transitions_per_cycle = options.ports,
ruby_system = ruby_system)
exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index 124845ab8..819834f56 100644
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -107,6 +107,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
options.allow_atomic_migration,
send_evictions = (
options.cpu_type == "detailed"),
+ transitions_per_cycle = options.ports,
ruby_system = ruby_system)
cpu_seq = RubySequencer(version = i,
@@ -196,6 +197,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
memBuffer = mem_cntrl,
probe_filter_enabled = options.pf_on,
full_bit_dir_enabled = options.dir_on,
+ transitions_per_cycle = options.ports,
ruby_system = ruby_system)
if options.recycle_latency:
@@ -216,6 +218,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
dma_cntrl = DMA_Controller(version = i,
cntrl_id = cntrl_count,
dma_sequencer = dma_seq,
+ transitions_per_cycle = options.ports,
ruby_system = ruby_system)
exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index b6cc7a5e8..e9a8a3c3f 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -52,6 +52,11 @@ def define_options(parser):
default='2GHz',
help="Clock for blocks running at Ruby system's speed")
+ # Options related to cache structure
+ parser.add_option("--ports", action="store", type="int", default=4,
+ help="used of transitions per cycle which is a proxy \
+ for the number of ports.")
+
# ruby network options
parser.add_option("--topology", type="string", default="Crossbar",
help="check src/mem/ruby/network/topologies for complete set")