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authorMitch Hayenga <mitch.hayenga@arm.com>2015-09-30 11:14:19 -0500
committerMitch Hayenga <mitch.hayenga@arm.com>2015-09-30 11:14:19 -0500
commita5c4eb3de9deb3a71a6a5230a25ff5962e584980 (patch)
tree874b659c6a5eaa1316cde9eb82ec7d08badf638a /configs
parente255fa053f8d105de8d188077a318124a3aad9ce (diff)
downloadgem5-a5c4eb3de9deb3a71a6a5230a25ff5962e584980.tar.xz
isa,cpu: Add support for FS SMT Interrupts
Adds per-thread interrupt controllers and thread/context logic so that interrupts properly get routed in SMT systems.
Diffstat (limited to 'configs')
-rw-r--r--configs/example/fs.py6
-rw-r--r--configs/example/se.py6
2 files changed, 6 insertions, 6 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 70a3b950e..9d8b87aaa 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -176,9 +176,9 @@ def build_test_system(np):
cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
- cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master
- cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave
- cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master
+ cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
+ cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave
+ cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master
else:
if options.caches or options.l2cache:
diff --git a/configs/example/se.py b/configs/example/se.py
index afd916cdb..0928482b7 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -265,9 +265,9 @@ if options.ruby:
system.cpu[i].icache_port = ruby_port.slave
system.cpu[i].dcache_port = ruby_port.slave
if buildEnv['TARGET_ISA'] == 'x86':
- system.cpu[i].interrupts.pio = ruby_port.master
- system.cpu[i].interrupts.int_master = ruby_port.slave
- system.cpu[i].interrupts.int_slave = ruby_port.master
+ system.cpu[i].interrupts[0].pio = ruby_port.master
+ system.cpu[i].interrupts[0].int_master = ruby_port.slave
+ system.cpu[i].interrupts[0].int_slave = ruby_port.master
system.cpu[i].itb.walker.port = ruby_port.slave
system.cpu[i].dtb.walker.port = ruby_port.slave
else: