summaryrefslogtreecommitdiff
path: root/configs
diff options
context:
space:
mode:
authorKevin Lim <ktlim@umich.edu>2006-06-16 17:08:47 -0400
committerKevin Lim <ktlim@umich.edu>2006-06-16 17:08:47 -0400
commitbaba18ab9214d1fe2236cd932c3bfca5ddfb06d6 (patch)
tree79bbaa1e8fffb520730ab514cce8463ca24ada09 /configs
parent720e6c4145726d310aa19fed4f48bf6a8e32912e (diff)
downloadgem5-baba18ab9214d1fe2236cd932c3bfca5ddfb06d6.tar.xz
Two updates that got combined into one ChangeSet accidentally. They're both pretty simple so they shouldn't cause any trouble.
First: Rename FullCPU and its variants in the o3 directory to O3CPU to differentiate from the old model, and also to specify it's an out of order model. Second: Include build options for selecting the Checker to be used. These options make sure if the Checker is being used there is a CPU that supports it also being compiled. SConstruct: Add in option USE_CHECKER to allow for not compiling in checker code. The checker is enabled through this option instead of through the CPU_MODELS list. However it's still necessary to treat the Checker like a CPU model, so it is appended onto the CPU_MODELS list if enabled. configs/test/test.py: Name change for DetailedCPU to DetailedO3CPU. Also include option for max tick. src/base/traceflags.py: Add in O3CPU trace flag. src/cpu/SConscript: Rename AlphaFullCPU to AlphaO3CPU. Only include checker sources if they're necessary. Also add a list of CPUs that support the Checker, and only allow the Checker to be compiled in if one of those CPUs are also being included. src/cpu/base_dyn_inst.cc: src/cpu/base_dyn_inst.hh: Rename typedef to ImplCPU instead of FullCPU, to differentiate from the old FullCPU. src/cpu/cpu_models.py: src/cpu/o3/alpha_cpu.cc: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_builder.cc: src/cpu/o3/alpha_cpu_impl.hh: Rename AlphaFullCPU to AlphaO3CPU to differentiate from old FullCPU model. src/cpu/o3/alpha_dyn_inst.hh: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/alpha_impl.hh: src/cpu/o3/alpha_params.hh: src/cpu/o3/commit.hh: src/cpu/o3/cpu.hh: src/cpu/o3/decode.hh: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch.hh: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_impl.hh: src/cpu/o3/lsq_unit.hh: src/cpu/o3/regfile.hh: src/cpu/o3/rename.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/rob.hh: src/cpu/o3/rob_impl.hh: src/cpu/o3/thread_state.hh: src/python/m5/objects/AlphaO3CPU.py: Rename FullCPU to O3CPU to differentiate from old FullCPU model. src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_unit_impl.hh: Rename FullCPU to O3CPU to differentiate from old FullCPU model. Also #ifdef the checker code so it doesn't need to be included if it's not selected. --HG-- rename : src/cpu/checker/o3_cpu_builder.cc => src/cpu/checker/o3_builder.cc rename : src/cpu/checker/cpu_builder.cc => src/cpu/checker/ozone_builder.cc rename : src/python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaO3CPU.py extra : convert_revision : 86619baf257b8b7c8955efd447eba56e0d7acd6a
Diffstat (limited to 'configs')
-rw-r--r--configs/test/test.py8
1 files changed, 6 insertions, 2 deletions
diff --git a/configs/test/test.py b/configs/test/test.py
index 2ece9e675..05fdb7786 100644
--- a/configs/test/test.py
+++ b/configs/test/test.py
@@ -14,6 +14,7 @@ parser = optparse.OptionParser(option_list=m5.standardOptions)
parser.add_option("-c", "--cmd", default="hello")
parser.add_option("-t", "--timing", action="store_true")
parser.add_option("-f", "--full", action="store_true")
+parser.add_option("-m", "--maxtick", type="int")
(options, args) = parser.parse_args()
@@ -34,7 +35,7 @@ mem = PhysicalMemory()
if options.timing:
cpu = TimingSimpleCPU()
elif options.full:
- cpu = DetailedCPU()
+ cpu = DetailedO3CPU()
else:
cpu = AtomicSimpleCPU()
cpu.workload = process
@@ -48,7 +49,10 @@ root = Root(system = system)
m5.instantiate(root)
# simulate until program terminates
-exit_event = m5.simulate()
+if options.maxtick:
+ exit_event = m5.simulate(options.maxtick)
+else:
+ exit_event = m5.simulate()
print 'Exiting @', m5.curTick(), 'because', exit_event.getCause()