Add in files from merge-bare-iron, get them compiling in FS and SE mode

--HG--
extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251

2 files changed, 112 insertions, 1 deletions

diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 78be4fc3a..ea6e52775 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -52,7 +52,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
     self.iobus = Bus(bus_id=0)
     self.membus = Bus(bus_id=1)
     self.bridge = Bridge(delay='50ns', nack_delay='4ns')
-    self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
+    self.physmem = PhysicalMemory(range = AddrRange('64MB'))
     self.bridge.side_a = self.iobus.port
     self.bridge.side_b = self.membus.port
     self.physmem.port = self.membus.port
@@ -118,6 +118,43 @@ def makeSparcSystem(mem_mode, mdesc = None):
 
     return self
 
+def makeLinuxMipsSystem(mem_mode, mdesc = None):
+    class BaseMalta(Malta):
+        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
+        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
+                            pci_func=0, pci_dev=0, pci_bus=0)
+
+    self = LinuxMipsSystem()
+    if not mdesc:
+        # generic system
+        mdesc = SysConfig()
+    self.readfile = mdesc.script()
+    self.iobus = Bus(bus_id=0)
+    self.membus = Bus(bus_id=1)
+    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
+    self.physmem = PhysicalMemory(range = AddrRange('1GB'))
+    self.bridge.side_a = self.iobus.port
+    self.bridge.side_b = self.membus.port
+    self.physmem.port = self.membus.port
+    self.disk0 = CowIdeDisk(driveID='master')
+    self.disk2 = CowIdeDisk(driveID='master')
+    self.disk0.childImage(mdesc.disk())
+    self.disk2.childImage(disk('linux-bigswap2.img'))
+    self.malta = BaseMalta()
+    self.malta.attachIO(self.iobus)
+    self.malta.ide.pio = self.iobus.port
+    self.malta.ethernet.pio = self.iobus.port
+    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
+                                               read_only = True))
+    self.intrctrl = IntrControl()
+    self.mem_mode = mem_mode
+    self.sim_console = SimConsole()
+    self.kernel = binary('mips/vmlinux')
+    self.console = binary('mips/console')
+    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
+
+    return self
+
 def makeX86System(mem_mode, mdesc = None):
     self = X86System()
     if not mdesc:
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 74ee875a3..0ac05338f 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -97,6 +97,8 @@ else:
 
 if m5.build_env['TARGET_ISA'] == "alpha":
     test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
+elif m5.build_env['TARGET_ISA'] == "mips":
+    test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
 elif m5.build_env['TARGET_ISA'] == "sparc":
     test_sys = makeSparcSystem(test_mem_mode, bm[0])
 elif m5.build_env['TARGET_ISA'] == "x86":
@@ -140,9 +142,81 @@ for i in xrange(np):
     if options.fastmem:
         test_sys.cpu[i].physmem_port = test_sys.physmem.port
 
+if m5.build_env['TARGET_ISA'] == 'mips':
+        #CP0 Configuration
+        TestCPUClass.CP0_PRId_CompanyOptions = 0
+        TestCPUClass.CP0_PRId_CompanyID = 1
+        TestCPUClass.CP0_PRId_ProcessorID = 147
+        TestCPUClass.CP0_PRId_Revision = 0
+
+        #CP0 Interrupt Control
+        TestCPUClass.CP0_IntCtl_IPTI = 7
+        TestCPUClass.CP0_IntCtl_IPPCI = 7
+
+        # Config Register
+        #TestCPUClass.CP0_Config_K23 = 0 # Since TLB
+        #TestCPUClass.CP0_Config_KU = 0 # Since TLB
+        TestCPUClass.CP0_Config_BE = 0 # Little Endian
+        TestCPUClass.CP0_Config_AR = 1 # Architecture Revision 2
+        TestCPUClass.CP0_Config_AT = 0 # MIPS32
+        TestCPUClass.CP0_Config_MT = 1 # TLB MMU
+        #TestCPUClass.CP0_Config_K0 = 2 # Uncached
+
+        #Config 1 Register
+        TestCPUClass.CP0_Config1_M = 1 # Config2 Implemented
+        TestCPUClass.CP0_Config1_MMU = 63 # TLB Size
+        # ***VERY IMPORTANT***
+        # Remember to modify CP0_Config1 according to cache specs
+        # Examine file ../common/Cache.py
+        TestCPUClass.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
+        TestCPUClass.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
+        TestCPUClass.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
+        TestCPUClass.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
+        TestCPUClass.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
+        TestCPUClass.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
+        TestCPUClass.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
+        TestCPUClass.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
+        TestCPUClass.CP0_Config1_PC = 1 # Performance Counters Implemented
+        TestCPUClass.CP0_Config1_WR = 0 # Watch Registers Implemented
+        TestCPUClass.CP0_Config1_CA = 0 # Mips16e NOT implemented
+        TestCPUClass.CP0_Config1_EP = 0 # EJTag Not Implemented
+        TestCPUClass.CP0_Config1_FP = 0 # FPU Implemented
+
+        #Config 2 Register
+        TestCPUClass.CP0_Config2_M = 1 # Config3 Implemented
+        TestCPUClass.CP0_Config2_TU = 0 # Tertiary Cache Control
+        TestCPUClass.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
+        TestCPUClass.CP0_Config2_TL = 0 # Tertiary Cache Line Size
+        TestCPUClass.CP0_Config2_TA = 0 # Tertiary Cache Associativity
+        TestCPUClass.CP0_Config2_SU = 0 # Secondary Cache Control
+        TestCPUClass.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
+        TestCPUClass.CP0_Config2_SL = 0 # Secondary Cache Line Size
+        TestCPUClass.CP0_Config2_SA = 0 # Secondary Cache Associativity
+
+
+        #Config 3 Register
+        TestCPUClass.CP0_Config3_M = 0 # Config4 Not Implemented
+        TestCPUClass.CP0_Config3_DSPP = 1 # DSP ASE Present
+        TestCPUClass.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
+        TestCPUClass.CP0_Config3_VEIC = 0 # EIC Supported
+        TestCPUClass.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
+        TestCPUClass.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
+        TestCPUClass.CP0_Config3_MT = 0 # MT Not present
+        TestCPUClass.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
+        TestCPUClass.CP0_Config3_TL = 0 # TraceLogic Not implemented
+
+        #SRS Ctl - HSS
+        TestCPUClass.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
+
+
+        #TestCPUClass.tlb = TLB()
+        #TestCPUClass.UnifiedTLB = 1
+
 if len(bm) == 2:
     if m5.build_env['TARGET_ISA'] == 'alpha':
         drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
+    elif m5.build_env['TARGET_ISA'] == 'mips':
+        drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
     elif m5.build_env['TARGET_ISA'] == 'sparc':
         drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
     elif m5.build.env['TARGET_ISA'] == 'x86':