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authorAndreas Sandberg <Andreas.Sandberg@arm.com>2013-01-07 13:05:35 -0500
committerAndreas Sandberg <Andreas.Sandberg@arm.com>2013-01-07 13:05:35 -0500
commit3db3f83a5ea4b9565db1ab6b22d18e2b33ecef98 (patch)
treea736f3746d5c38bdc98d6fb8589113556271d486 /configs
parent69d419f31383ac7801e1debb62d5bbf7cb899e3c (diff)
downloadgem5-3db3f83a5ea4b9565db1ab6b22d18e2b33ecef98.tar.xz
arch: Make the ISA class inherit from SimObject
The ISA class on stores the contents of ID registers on many architectures. In order to make reset values of such registers configurable, we make the class inherit from SimObject, which allows us to use the normal generated parameter headers. This patch introduces a Python helper method, BaseCPU.createThreads(), which creates a set of ISAs for each of the threads in an SMT system. Although it is currently only needed when creating multi-threaded CPUs, it should always be called before instantiating the system as this is an obvious place to configure ID registers identifying a thread/CPU.
Diffstat (limited to 'configs')
-rw-r--r--configs/example/fs.py2
-rw-r--r--configs/example/ruby_fs.py1
-rw-r--r--configs/example/se.py2
3 files changed, 5 insertions, 0 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py
index f1b8acedf..9b8ae1d29 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -139,6 +139,7 @@ for i in xrange(np):
test_sys.cpu[i].fastmem = True
if options.checker:
test_sys.cpu[i].addCheckerCpu()
+ test_sys.cpu[i].createThreads()
CacheConfig.config_cache(options, test_sys)
@@ -155,6 +156,7 @@ if len(bm) == 2:
drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
drive_sys.cpu = DriveCPUClass(cpu_id=0)
+ drive_sys.cpu.createThreads()
drive_sys.cpu.createInterruptController()
drive_sys.cpu.connectAllPorts(drive_sys.membus)
if options.fastmem:
diff --git a/configs/example/ruby_fs.py b/configs/example/ruby_fs.py
index 97863a46b..8d21cfb32 100644
--- a/configs/example/ruby_fs.py
+++ b/configs/example/ruby_fs.py
@@ -103,6 +103,7 @@ for (i, cpu) in enumerate(system.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
+ cpu.createThreads()
cpu.createInterruptController()
cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
diff --git a/configs/example/se.py b/configs/example/se.py
index c4c6daedf..fe5524ef5 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -180,6 +180,8 @@ for i in xrange(np):
if options.checker:
system.cpu[i].addCheckerCpu()
+ system.cpu[i].createThreads()
+
if options.ruby:
if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"