mem: Update DRAM configuration names

Names of DRAM configurations were updated to reflect both
the channel and device data width.

Previous naming format was:
	<DEVICE_TYPE>_<DATA_RATE>_<CHANNEL_WIDTH>

The following nomenclature is now used:
	<DEVICE_TYPE>_<DATA_RATE>_<n>x<w>
where n = The number of devices per rank on the channel
      x = Device width

Total channel width can be calculated by n*w

Example:
A 64-bit DDR4, 2400 channel consisting of 4-bit devices:
	n = 16
	w = 4
The resulting configuration name is:
	DDR4_2400_16x4

Updated scripts to match new naming convention.

Added unique configurations for DDR4 for:
1) 16x4
2) 8x8
3) 4x16

Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>

9 files changed, 12 insertions, 12 deletions

diff --git a/configs/common/HMC.py b/configs/common/HMC.py
index fcff94cc7..e43cbddfc 100644
--- a/configs/common/HMC.py
+++ b/configs/common/HMC.py
@@ -58,7 +58,7 @@
 # serial links, the main internal crossbar, and an external hmc controller.
 #
 # - VAULT CONTROLLERS:
-#   Instances of the HMC_2500_x32 class with their functionality specified in
+#   Instances of the HMC_2500_1x32 class with their functionality specified in
 #   dram_ctrl.cc
 #
 # - THE MAIN XBAR:
diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index 2cfa25e58..b625084cb 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -152,7 +152,7 @@ def config_mem(options, system):
     them.
     """
 
-    if ( options.mem_type == "HMC_2500_x32"):
+    if ( options.mem_type == "HMC_2500_1x32"):
         HMChost = HMC.config_host_hmc(options, system)
         HMC.config_hmc(options, system, HMChost.hmc_host)
         subsystem = system.hmc_dev
@@ -223,7 +223,7 @@ def config_mem(options, system):
 
     # Connect the controllers to the membus
     for i in xrange(len(subsystem.mem_ctrls)):
-        if (options.mem_type == "HMC_2500_x32"):
+        if (options.mem_type == "HMC_2500_1x32"):
             subsystem.mem_ctrls[i].port = xbar[i/4].master
         else:
             subsystem.mem_ctrls[i].port = xbar.master
diff --git a/configs/common/Options.py b/configs/common/Options.py
index a3335c7ef..9af15ff2f 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -77,7 +77,7 @@ def addNoISAOptions(parser):
     parser.add_option("--list-mem-types",
                       action="callback", callback=_listMemTypes,
                       help="List available memory types")
-    parser.add_option("--mem-type", type="choice", default="DDR3_1600_x64",
+    parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8",
                       choices=MemConfig.mem_names(),
                       help = "type of memory to use")
     parser.add_option("--mem-channels", type="int", default=1,
diff --git a/configs/dram/lat_mem_rd.py b/configs/dram/lat_mem_rd.py
index f148656f2..ddc44e229 100644
--- a/configs/dram/lat_mem_rd.py
+++ b/configs/dram/lat_mem_rd.py
@@ -80,7 +80,7 @@ except:
 
 parser = optparse.OptionParser()
 
-parser.add_option("--mem-type", type="choice", default="DDR3_1600_x64",
+parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8",
                   choices=MemConfig.mem_names(),
                   help = "type of memory to use")
 parser.add_option("--mem-size", action="store", type="string",
diff --git a/configs/dram/sweep.py b/configs/dram/sweep.py
index ac232a8fd..32cf00345 100644
--- a/configs/dram/sweep.py
+++ b/configs/dram/sweep.py
@@ -53,8 +53,8 @@ from common import MemConfig
 
 parser = optparse.OptionParser()
 
-# Use a single-channel DDR3-1600 x64 by default
-parser.add_option("--mem-type", type="choice", default="DDR3_1600_x64",
+# Use a single-channel DDR3-1600 x64 (8x8 topology) by default
+parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8",
                   choices=MemConfig.mem_names(),
                   help = "type of memory to use")
 
diff --git a/configs/example/hmctest.py b/configs/example/hmctest.py
index 6e1ad457b..3e0fa124a 100644
--- a/configs/example/hmctest.py
+++ b/configs/example/hmctest.py
@@ -13,8 +13,8 @@ from common import HMC
 
 parser = optparse.OptionParser()
 
-# Use a HMC_2500_x32 by default
-parser.add_option("--mem-type", type = "choice", default = "HMC_2500_x32",
+# Use a HMC_2500_1x32 (1 channel, 32-bits wide) by default
+parser.add_option("--mem-type", type = "choice", default = "HMC_2500_1x32",
                   choices = MemConfig.mem_names(),
                   help = "type of memory to use")
 
diff --git a/configs/example/memcheck.py b/configs/example/memcheck.py
index 7ef413389..0bbcd2f7c 100644
--- a/configs/example/memcheck.py
+++ b/configs/example/memcheck.py
@@ -216,7 +216,7 @@ cfg_file.close()
 proto_tester = TrafficGen(config_file = cfg_file_name)
 
 # Set up the system along with a DRAM controller
-system = System(physmem = DDR3_1600_x64())
+system = System(physmem = DDR3_1600_8x8())
 
 system.voltage_domain = VoltageDomain(voltage = '1V')
 
diff --git a/configs/learning_gem5/part1/simple.py b/configs/learning_gem5/part1/simple.py
index 1249a8464..393240a66 100644
--- a/configs/learning_gem5/part1/simple.py
+++ b/configs/learning_gem5/part1/simple.py
@@ -75,7 +75,7 @@ if m5.defines.buildEnv['TARGET_ISA'] == "x86":
     system.cpu.interrupts[0].int_slave = system.membus.master
 
 # Create a DDR3 memory controller and connect it to the membus
-system.mem_ctrl = DDR3_1600_x64()
+system.mem_ctrl = DDR3_1600_8x8()
 system.mem_ctrl.range = system.mem_ranges[0]
 system.mem_ctrl.port = system.membus.master
 
diff --git a/configs/learning_gem5/part1/two_level.py b/configs/learning_gem5/part1/two_level.py
index 878baa312..3dcb71a51 100644
--- a/configs/learning_gem5/part1/two_level.py
+++ b/configs/learning_gem5/part1/two_level.py
@@ -128,7 +128,7 @@ if m5.defines.buildEnv['TARGET_ISA'] == "x86":
 system.system_port = system.membus.slave
 
 # Create a DDR3 memory controller
-system.mem_ctrl = DDR3_1600_x64()
+system.mem_ctrl = DDR3_1600_8x8()
 system.mem_ctrl.range = system.mem_ranges[0]
 system.mem_ctrl.port = system.membus.master