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authorGabe Black <gblack@eecs.umich.edu>2007-10-07 17:52:36 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-10-07 17:52:36 -0700
commit847a18ad48445a3b4f8fa9b8f8c2594a8a952f84 (patch)
tree093a95a648bacbe0a588a9bc0be921285072321b /configs
parente540c37282467e62ff457fdd39ca2f584fdfd10c (diff)
downloadgem5-847a18ad48445a3b4f8fa9b8f8c2594a8a952f84.tar.xz
X86: Adjust the config scripts for x86 fs.
--HG-- extra : convert_revision : 36ed22b50066f54be0e51c3419babc07dd218e10
Diffstat (limited to 'configs')
-rw-r--r--configs/common/FSConfig.py19
-rw-r--r--configs/example/fs.py4
2 files changed, 23 insertions, 0 deletions
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 2ab214dc5..78be4fc3a 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -118,6 +118,25 @@ def makeSparcSystem(mem_mode, mdesc = None):
return self
+def makeX86System(mem_mode, mdesc = None):
+ self = X86System()
+ if not mdesc:
+ # generic system
+ mdesc = SysConfig()
+ self.readfile = mdesc.script()
+
+ # Physical memory
+ self.membus = Bus(bus_id=0)
+ self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
+ self.physmem.port = self.membus.port
+
+ # Platform
+ self.opteron = Opteron()
+
+ self.intrctrl = IntrControl()
+
+ return self
+
def makeDualRoot(testSystem, driveSystem, dumpfile):
self = Root()
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 3a57fe5b8..ea525bf41 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -99,6 +99,8 @@ if m5.build_env['TARGET_ISA'] == "alpha":
test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
elif m5.build_env['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0])
+elif m5.build_env['TARGET_ISA'] == "x86":
+ test_sys = makeX86System(test_mem_mode, bm[0])
else:
m5.panic("incapable of building non-alpha or non-sparc full system!")
@@ -140,6 +142,8 @@ if len(bm) == 2:
drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
elif m5.build_env['TARGET_ISA'] == 'sparc':
drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
+ elif m5.build.env['TARGET_ISA'] == 'x86':
+ drive_sys = makeX86System(drive_mem_mode, bm[1])
drive_sys.cpu = DriveCPUClass(cpu_id=0)
drive_sys.cpu.connectMemPorts(drive_sys.membus)
if options.fastmem: